Patching of Programmable Memory

• US 20150046630A1
• Filed: 08/07/2013
• Published: 02/12/2015
• Est. Priority Date: 08/07/2013
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: Cambridge Silicon Radio Limited (Qualcomm, Inc.)
• Inventors: Hoayun, Paul
• Granted Patent: US 10,453,534 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 8/66 of program code stored in read-only memory [ROM]
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing

Abstract

A programmable memory 10 comprises programmable data bit cells. A data word comprises a group of the programmable data bit cells. A method of configuring patch code in the memory 10 comprises identifying a first location (e.g. 0x1234) in the programmable memory 10 where a patch is required; modifying a data word at the first location to a predetermined data value (e.g. 0xFFFF); writing patch code for the patch at a patch code location (e.g. 0xABCD); and storing the patch code location. The predetermined data value can be, or can map to, a value of an exception instruction of the processor 20 which will cause the processor 20 to read from a patch table 14. The programmable memory 10 can be a One Time Programmable (OTP) memory.

Claims

1. A method of configuring patch code for a programmable memory, the programmable memory comprising programmable data bit cells, wherein a data word comprises a group of the programmable data bit cells, the method comprising:

identifying a first location in the programmable memory where a patch is required;

modifying a data word at the first location to a predetermined data value;

writing patch code for the patch at a patch code location; and

storing the patch code location.

2. The method according to claim 1, wherein the programmable memory is in communication with a processor.

3. A method according to claim 2 wherein the step of storing the patch code location comprises storing the patch code location in a patch table and the predetermined data value is a value of an exception instruction of the processor which will cause the processor to read from the patch table.

4. A method according to claim 2 wherein the step of storing the patch code location comprises storing the patch code location in a patch table and wherein the programmable memory is in communication with logic for mapping the predetermined data value to a value of an exception instruction of the processor which will cause the processor to read the patch table.

5. A method according to claim 3 wherein the step of storing the patch code location in a patch table further comprises storing a correspondence between the patch code location and the first location.

6. A method according to claim 1 wherein the step of storing the patch code location comprises storing the patch code location in a patch table and wherein the step of modifying a data word at the first location to a predetermined data value further comprises modifying subsequent data words at the first location to indicate a position of the patch code location in the patch table.

7. A method according to claim 6 wherein the position of the patch code location in the patch table is represented by a variable number of data words and the modifying subsequent data words comprises modifying the number of data words such that all of the data bit cells of the number of data words are in a programmed state.

8. A method according to claim 6 wherein a group of data words represent an index value which indicates the position of the patch code location in the patch table, wherein each bit of the index value is encoded by a different data word in the group of data words, and wherein one of the binary values of a bit of the index value is encoded by modifying the data word such that all of the data bit cells of the data word are in a programmed state.

9. A method according to claim 1 wherein the step of storing the patch code location comprises modifying subsequent data words at the first location to indicate the patch code location, where each bit of the patch code location is encoded by a different existing data word, and wherein one of the binary values of a bit of the patch code location is encoded by modifying the existing data word such that all of the data bit cells of the existing data word are in a programmed state.

10. A method according to claim 1 wherein the step of modifying a data word at the first location to a predetermined data value comprises modifying all of the data bit cells of the data word to a programmed state.

11. A method according to claim 1 wherein the step of writing patch code for the patch at a patch code location writes the patch code in the programmable memory.

12. A method of operating a system comprising a processor and a programmable memory, the method comprising:

reading a data word at a first location in the programmable memory;

determining if a value of the data word corresponds to an exception instruction of the processor;

if the value of the data word is determined to correspond to the exception instruction of the processor;

performing a look up in a patch table for a patch code location;

reading data at the patch code location.

13. A method according to claim 12 further comprising:

performing a logical operation on the data word read from the first location in the programmable memory to form a mapped value;

applying the mapped value to the processor

and wherein the step of determining if the value of the data word corresponds to an exception instruction of the processor is performed on the mapped value.

14. A method according to claim 12 wherein the patch table comprises a correspondence between the patch code location and the first location.

15. A method according to claim 12 further comprising reading subsequent data words at the first location to determine a position of the patch code location in the patch table.

16. A method according to claim 15 wherein the position of the patch code location in the patch table is represented by a variable number of data words and the method further comprises determining the number of data words.

17. A method according to claim 15 wherein a group of data words represent an index value which indicates the position of the patch code location in the patch table, wherein each bit of the index value is encoded by a different data word in the group of data words.

18. A system comprising:

a programmable memory comprising programmable data bit cells, wherein a data word comprises a group of the programmable data bit cells;

a processor which is arranged to access the programmable memory and which is arranged to;

identify a first location in the programmable memory where a patch is required;

modify a data word at the first location to a predetermined data value;

write patch code for the patch at a patch code location; and

store the patch code location.

19. A system according to claim 18 wherein the processor is arranged to:

read a data word at a first location in the programmable memory;

determine if a value of the data word corresponds to an exception instruction of the processor;

if the value of the data word is determined to correspond to the exception instruction of the processor;

perform a look up in a patch table for a patch code location;

read data at the patch code location.

20. A system according to claim 19 wherein the processor is arranged to:

perform a logical operation on the data word read from the first location in the programmable memory to form a mapped data value;

apply the mapped value to the processor;

and use the mapped value when determining if the value of the data word corresponds to an exception instruction of the processor.