MULTI-BIT MEMORY DEVICE AND ON-CHIP BUFFERED PROGRAM METHOD THEREOF

• US 20150046638A1
• Filed: 08/05/2014
• Published: 02/12/2015
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOI, Wan-Soo, KIM, Taec-Jun, NAM, Sang-Wook, LEE, Jae-Hwa
• Granted Patent: US 9,847,122 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A program method of a multi-bit memory device is provided. First page data is programmed in a first region of a memory cell array. The first page data is stored in a first buffer of a page buffer. Second page data is programmed in the first region of the memory cell array. The second page data is stored in a third buffer of the page buffer. Third page data is stored in the first region of the memory cell array. The second page data stored in the third buffer is transferred to a second buffer of the page buffer and the third page data is stored in the third buffer. The first to third page data stored in page buffer are programmed in a second region of the memory cell array.

Claims

1. A program method of a multi-bit memory device, the program method comprising:

programming first page data in a first region of a memory cell array;

storing the first page data in a first buffer of a page buffer;

programming second page data in the first region of the memory cell array;

storing the second page data in a third buffer of the page buffer;

programming third page data in the first region of the memory cell array;

transferring the second page data stored in the third buffer to a second buffer of the page buffer and then storing the third page data in the third buffer;

performing, based on the first to third page data stored in the page buffer, a first programming operation on a second region of the memory cell array.

2. The program method of claim 1, wherein the programming of the first to third page data in the first region of the memory cell array comprises temporarily storing the first to third page data to an input buffer of the page buffer and then transferring the first to third page data stored in the input buffer to the second buffer.

3. The program method of claim 2, wherein the programming of the first to third page data in the first region of the memory cell array further comprises transferring the first to third page data stored in the second buffer to an output buffer of the page buffer and programming the first region of the memory cell array based on the first to third page data transferred to the output buffer.

4. The program method of claim 2, wherein the storing of the first page data in the first buffer comprises transferring the first page data temporarily stored in the input buffer to the first buffer.

5. The program method of claim 2, wherein the storing of the second and third page data in the third buffer comprises transferring the second and third page data temporarily stored in the input buffer to the third buffer, respectively.

6. The program method of claim 1, further comprising after the performing of the second programming operation, performing a second programming operation on the second region of the memory cell array based on the first to third data programmed in the first region of the memory cell array.

7. The program method of claim 1, wherein the first region of the memory cell array includes a memory cell configured to store 1-bit data.

8. The program method of claim 1, wherein the second region of the memory cell array includes a memory cell configured to store M-bit data, where is a natural number of 3 or greater.

9. A multi-bit memory device comprising:

a first memory cell array region configured to store a page data;

a page buffer configured to store the page data stored in the first memory cell array region,

a second memory cell array region comprising a memory cell configured to be programmed using the page data stored in the page buffer.

10. The multi-bit memory device of claim 9, wherein after the memory cell of the second memory cell array region is programmed using the page data stored in the page buffer, the memory cell of the second memory cell array region is further programmed using the page data stored in the first memory cell array region.

11. The multi-bit memory device of claim 10, wherein the further programming of the memory cell in the second memory cell array region is performed using an incremental step pulse program (ISPP) algorithm.

12. The multi-bit memory device of claim 10, wherein the first memory cell array region is further configured to store another page data after the memory cell of the second memory cell array region is programmed using the page data stored in the page buffer, wherein another page is stored in the page buffer in place of the page data stored in the page buffer.

13. The multi-bit memory device of claim 10, wherein the page buffer includes first to third buffers, the page data includes first to third page data, and the first to third page data are stored in the first to third buffers, respectively.

14. The multi-bit memory device of claim 13, wherein the first memory cell array region includes a memory cell configured to store 1-bit data, and memory cell of the second region of the memory cell array is configured to store M-bit data, where M is a natural number of 3 or greater.

15. The multi-bit memory device of claim 13, wherein after the second page data is programmed in the first region of the memory cell array, the second page data is stored in the third buffer, and after the third page data is programmed in the first region of the memory cell array, the second page data stored in the third buffer is transferred to the second buffer and then the third page data is stored in the third buffer.

16. A program method of a multi-bit memory device, the program method comprising:

receiving a first data including at least three 1-bit data;

storing the first data in a first memory cell array region and a page buffer, wherein the first memory cell array region includes a plurality of memory cells whose each memory cell is configured to store an 1-bit data;

performing a first programming operation on a second memory cell array region based on the first data stored in the page buffer, wherein the second memory cell array region includes a plurality of memory cells whose each memory cell is configured to store a multi-level data representing the first data;

performing a second programming operation on the second memory cell array region based on the first data stored in the first memory cell array region.

17. The program method of claim 16, further comprising:

receiving a second data including at least three 1-bit data,

storing the second data in a first memory cell array region and the page buffer, wherein the first data stored in the page data is replaced with the second data; and

performing a first programming operation on the second memory cell array region based on the second data stored in the first memory cell array region,

wherein the storing the second data and performing of the first programming operation based on the second data occurs between performing the first and second programming operation based on the first data;

18. The program method of claim 16, wherein the second programming operation is performed using an incremental step pulse program (ISPP) algorithm.

19. The program method of claim 16, wherein the second data is received before the performing of the second programming operation based on the first data stored in the first memory cell array region.

20. The program method of claim 19, wherein the storing of the first data comprises:

storing a first 1-bit data of the at least three 1-bit data in an input buffer of the input buffer;

copying the first 1-bit data stored in the input buffer of the input buffer to an output buffer through a second buffer;

storing the first 1-bit data stored in the output buffer of the page buffer in the first memory cell;

and then, copying the first 1-bit data stored in the input buffer in a first buffer of the page buffer.