GLOBAL BRANCH PREDICTION USING BRANCH AND FETCH GROUP HISTORY

• US 20150046691A1
• Filed: 11/08/2013
• Published: 02/12/2015
• Est. Priority Date: 08/12/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Heil, Timothy H., Hilton, Andrew D.
• Granted Patent: US 9,921,846 B2
• Time in Patent Office: Days
• US Class Current: 712/240
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G06F 9/3848 using hybrid branch prediction, e.g. selection between prediction techniques
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

This disclosure includes a method for performing branch prediction by a processor having an instruction pipeline. The processor speculatively updates a global history register having fetch group history and branch history, fetches a fetch group of instructions, and assigns a global history vector to the instructions. The processor predicts any branches in the fetch group using the global history vector and a predictor, and evaluates whether the fetch group contains a predicted taken branch. If the fetch group contains a predicted taken branch, the processor flushes subsequently fetched instructions in the pipeline following the predicted taken branch, repairs the global history register to the global history vector, and updates the global history register based on branch prediction information. If the fetch group does not contain a predicted taken branch, the processor updates the global history register with a branch history value for each branch in the fetch group.

Claims

1. A computer system comprising:

an instruction pipeline circuit, comprising;

an address register for fetching instruction addresses;

an instruction cache for storing fetched instructions;

an instruction queue for storing decoded instructions;

a branch prediction circuit, comprising;

a global history register maintaining a global history vector, wherein the global history register comprises a fetch group history portion and a branch history portion;

a predictor for predicting a direction of any branches in the fetch group;

combination logic for combining an instruction from the instruction register with the global history vector for indexing into the predictor;

a global history update circuit, comprising;

a storage register for storing the global history vector associated with the fetch group; and

fetch group history check logic for;

speculatively updating the fetch group history of the global history register with a fetch group history value for the fetch group;

evaluating whether the fetch group contains a predicted taken branch;

flushing instructions from the instruction cache and instruction queue when the fetch group contains a taken branch;

repairing the global history register to the global history vector stored in the storage register when the fetch group contains a taken branch;

updating the fetch group history of the global history register based on branch prediction information from the predictor when the fetch group contains a taken branch; and

updating the branch history of the global history register with a branch history value for each branch in the fetch group when the fetch group does not contain a taken branch.

2. The computer system of claim 1, wherein:

the instruction pipeline circuit further comprises an instruction execution unit for;

resolving a branch in the fetch group;

updating the predictor with branch resolution information;

the global history update circuit further comprises branch history check logic for;

evaluating whether the branch prediction for the branch is correct;

flushing instructions from the instruction cache and instruction queue when the branch prediction is not correct;

repairing the global history register to the global history vector stored in the storage register when the branch prediction is not correct; and

updating the fetch group history of the global history register based on branch resolution information from the instruction execution unit when the branch prediction is not correct.

3. The computer system of claim 2, wherein the first number of fetch group history bits is equal to the number of cycles for the processor to perform branch prediction on an instruction.

4. The computer system of claim 2, wherein:

the storage register stores a branch counter for a number of branches in the fetch group; and

the branch history logic updates the branch counter based on branch resolution information.

5. The computer system of claim 2, wherein the predictor comprises a prediction history table having saturating counters.

6. The computer system of claim 5, wherein the combination logic comprises exclusive-OR logic that hashes together an instruction address from the instruction address register and the global history vector to index into the prediction history table.