RECONFIGURABLE CIRCUIT TO EMULATE SYSTEM CRITICAL PATHS

• US 20150046721A1
• Filed: 08/06/2013
• Published: 02/12/2015
• Est. Priority Date: 08/06/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Drake, Alan J., Hui, David T., Owczarczyk, Pawel, Tiner, Marshall D., Yuan, Xiaobin
• Granted Patent: US 9,298,250 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.

Claims

1. A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device, the circuit comprising:

a voltage divider network that provides a plurality of voltages;

a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage selectable from the received plurality of voltages; and

at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal, the delayed pulse signal having a delay magnitude controllable by the scaled supply voltage and the scaled ground voltage, the delayed pulse signal being used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor,

the frequency correction signal being applied to the clock source to maintain a frequency guardband for the clock signal of the microprocessor during the variation to the supply voltage.

2. The circuit of claim 1, wherein the voltage divider network comprises a plurality of resistors connected between the supply voltage of the microprocessor and a ground voltage of the microprocessor.

3. The circuit of claim 1, wherein:

the scaled ground voltage comprises a voltage value in a range of from about zero volts up to about the supply voltage; and

the scaled supply voltage comprises a voltage value in a range of from about twice the supply voltage down to about zero volts

4. The circuit of claim 1, wherein the selector device comprises a selector input that selects the scaled supply voltage and the scaled ground voltage from among the received plurality of voltages, the scaled supply voltage and the scaled ground voltage providing an increased frequency per supply voltage variation slope as a function of an increased scaling down, and the scaled supply voltage and the scaled ground voltage providing a decreased frequency per supply voltage variation slope as a function of an increased scaling up.

5. The circuit of claim 1, wherein each of the at least one delay element comprises:

a transmission gate; and

a logic gate coupled to the transmission gate.

6. The circuit of claim 5, wherein the transmission gate comprises an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) that enable and disable a signal transmission path between an input terminal and an output terminal, the scaled supply voltage being coupled to a gate of the NFET, the scaled ground voltage being coupled to a gate of the PFET, and the clock signal being coupled to the input terminal for transmission to the output terminal.

7. The circuit of claim 6, wherein the logic gate comprises an inverter having an input and an output, the inverter providing a finite propagation delay between the input and the output.

8. The circuit of claim 1, further comprising:

an edge detector circuit that receives the delayed pulse signal and each pulse of the clock signal, wherein the edge detector generates a multi-bit code based on the delay magnitude of the delayed pulse signal relative to each pulse of the received clock signal.

9. The circuit of claim 8, further comprising:

a digital phase locked loop that receives the multi-bit code from the edge detector and generates the frequency correction signal that is applied to the clock source.

10. A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device, the circuit comprising:

a voltage divider network that provides a plurality of voltages;

a selector device that receives the plurality of voltages and provides a scaled supply voltage selectable from the received plurality of voltages; and

a delay path that receives the scaled supply voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal, the delayed pulse signal having a delay magnitude controllable by the scaled supply voltage, the delayed pulse signal being used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor,

the frequency correction signal being applied to the clock signal to maintain a frequency guardband for the clock signal of the microprocessor during the variation to the supply voltage.

11. The circuit of claim 10, wherein the delay path comprises:

a buffer amplifier that receives the scaled supply voltage and generates a buffered scaled supply voltage; and

at least one delay element having a voltage supply that receives the buffered scaled supply voltage, the at least one delay element providing the delay magnitude based on the buffered scaled supply voltage.

12. The circuit of claim 11, wherein the at least one delay element comprises at least one of an inverter, a NAND gate, and a NOR gate.

13. The circuit of claim 10, wherein:

the buffered scaled supply voltage comprises a voltage value in a range of from about two times the supply voltage down to about 0 volts.

14. The circuit of claim 10, wherein the selector device comprises a selector input that selects the scaled supply voltage from among the received plurality of voltages, the scaled supply voltage providing an increased frequency per supply voltage variation slope as a function of an increased scaling down, and the scaled supply voltage providing a decreased frequency per supply voltage variation slope as a function of an increased scaling up.

15. The circuit of claim 10, wherein the voltage divider network comprises a plurality of resistors connected between the supply voltage of the microprocessor and a ground voltage of the microprocessor.

16. A method of monitoring and controlling a clock signal generated by a clock source in a microprocessor device, the method comprising:

generating a plurality of scaled voltages;

selecting at least one scaled voltage from the generated plurality of scaled voltages;

applying the at least one scaled voltage to at least one delay element;

delaying each pulse of the clock signal propagating through the at least one delay element based on the selected at least one scaled voltage;

generating a frequency correction signal from the delaying of each pulse of the clock signal based on a variation to a supply voltage of the microprocessor; and

applying the frequency correction signal to the clock source for maintaining a frequency guardband for the clock signal of the microprocessor during the variation to the supply voltage.

17. The method of claim 16, wherein the selecting of the at least one scaled voltage provides an increased frequency per supply voltage variation slope as a function of an increased scaling down.

18. The method of claim 17, wherein the selecting of the at least one scaled voltage provides a decreased frequency per supply voltage variation slope as a function of an increased scaling up.

19. The method of claim 16, further comprising:

generating a multi-bit code based on the delaying of each pulse of the clock signal; and

generating the frequency correction signal that is applied to the clock source based on the multi-bit code.

20. The method of claim 16, wherein the generating of the plurality of scaled voltages comprises generating a voltage value in a range of from about twice the supply voltage down to about 0 volts.