EMBEDDED SOFTWARE DEBUG SYSTEM WITH PARTIAL HARDWARE ACCELERATION

• US 20150046753A1
• Filed: 08/09/2013
• Published: 02/12/2015
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Cecka, Kenneth E., Woodward, James T.
• Granted Patent: US 9,477,579 B2
• Time in Patent Office: Days
• US Class Current: 714/38.1
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

An embedded software debug system with partial hardware acceleration includes a computer that executes a debug software stack. The debug software stack includes high level operations. The system also includes a remote microcontroller electronically connected to the computer. The system further includes an embedded processor electronically connected to the remote microcontroller. The remote microcontroller receives an applet from the computer and executes the applet in conjunction with the computer executing the debug software stack to debug the embedded processor. The applet includes low level protocol operations including performance critical tight-loops precompiled into machine code. The debug software stack may include a stub that replaces the tight-loops of the applet. The computer may send the applet to the remote microcontroller in response to executing the still).

Claims

1. An embedded software debug system comprising:

an embedded processor configured to execute embedded software instructions;

a computing system comprising a processor configured to execute a debug software stack, wherein the debug software stack comprises a set of instructions for debugging the embedded software instructions; and

a remote microcontroller, communicatively coupled to the computing system and the embedded processor, and configured to;

receive an applet from the computing system wherein the applet comprises a subset of the set of instructions for debugging the embedded software instructions; and

execute the applet to debug the embedded software instructions executed on the embedded processor.

2. The system of claim 1 wherein said debug software stack comprises high level debug commands compiled and executed on said computer.

3. The system of claim 1 wherein said applet comprises low level protocol operations.

4. The system of claim 3 wherein said applet comprises source code compiled into native microcontroller machine code executed by the remote microcontroller.

5. The system of claim 1 wherein said remote microcontroller comprises a server, wherein said server accepts and executes said applet.

6. The system of claim 5 wherein said server of said microcontroller caches a most recent executed applet in a memory.

7. The system of claim 5 wherein said server comprises sufficient memory to cache multiple applets.

8. The system of claim 1 wherein said remote microcontroller comprises a core on a chip, wherein the chip comprises said embedded processor.

9. A method for debugging embedded software instructions executing on an embedded processor using an embedded software debug system, said method comprising:

executing a debug software stack by a computing system, wherein the debug software stack comprises a set of instructions for debugging the embedded software instructions on an embedded processor;

sending an applet to a remote microcontroller from said computing system through a high-latency connection, wherein the applet is a subset of the set of instructions for debugging the embedded software instructions;

executing said applet by said remote microcontroller and sending and receiving data between said remote microcontroller and said embedded processor through a low-latency connection in response to executing said applet; and

debugging said embedded processor in response to executing said debug software stack and said applet.

10. The method of claim 9 further comprising funning the applet, wherein the computing system automatically identifies flagged low level protocol operations of the debug software stack and compiles the low level protocol operations into a subset of the set of instructions for debugging the embedded software instructions to form the applet.

11. The method of claim 10 further comprising replacing the subset of the set of instructions forming the applet with a stub, wherein the stub comprises instructions for sending the applet.

12. The method of claim 11 wherein said sending said applet to said remote microcontroller further comprises performing said sending said applet in response to executing said stub by said computer.

13. The method of claim 9 further comprising compiling said applet into native microcontroller machine code for the remote microcontroller.

14. The method of claim 9 additionally comprising caching a most recent executed applet on a server of said remote microcontroller.

15. The method of claim 9 additionally comprising caching multiple applets on said server of said remote microcontroller.

16. The method of claim 9 wherein executing said applet by said remote microcontroller additionally comprises progressively streaming data to said applet.

17. An embedded software debug system comprising:

an embedded processor configured to execute embedded software instructions;

a computer comprising a processor configured to execute a debug software. stack, wherein the debug software stack comprises a set of instructions for debugging the embedded software instructions; and

a remote microcontroller, communicatively coupled to the computer through a high-latency connection and the embedded processor through a low-latency connection, and configured to;

receive an applet from the computer in response to execution of a stub of the debug software stack, wherein the applet comprises a subset of the set of instructions for debugging the embedded software instructions and the stub replaces the subset of the set of instructions forming the applet, and

execute the applet to debug the embedded software instructions executed on the embedded processor.

18. The system of claim 17 wherein said remote microcontroller comprises a server for caching multiple applets.

19. The system of claim 17 wherein said remote microcontroller comprises a core on a chip, wherein the chip comprises said embedded processor.

20. The system of claim 19 wherein said chip comprises a plurality of embedded processors and said remote microcontroller that is a core on said chip is electronically connected to the plurality of embedded processors for debugging.