SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR COLUMNS

• US 20150048441A1
• Filed: 08/16/2013
• Published: 02/19/2015
• Est. Priority Date: 08/16/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Ching, Kuo-Cheng, Guo, Ta-Pen, Diaz, Carlos H.
• Granted Patent: US 9,978,863 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.

Claims

1. A semiconductor arrangement comprising:

a substrate region;

a first semiconductor column projecting from the substrate region; and

a second semiconductor column projecting from the substrate region, the second semiconductor column separated a first distance from the first semiconductor column, the first distance between about 10 nm to about 30 nm.

2. The semiconductor arrangement of claim 1, wherein a cross-section of the first semiconductor column is substantially circular.

3. The semiconductor arrangement of claim 1, wherein the second semiconductor column is separated the first distance from the first semiconductor column along a first axis.

4. The semiconductor arrangement of claim 3, comprising a fourth semiconductor column projecting from the substrate region, the fourth semiconductor column separated the first distance from the first semiconductor column.

5. The semiconductor arrangement of claim 4, wherein the fourth semiconductor column is separated the first distance from the first semiconductor column along the first axis.

6. The semiconductor arrangement of claim 3, comprising a fifth semiconductor column projecting from the substrate region, the fifth semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis.

7. The semiconductor arrangement of claim 1, wherein a first cross-sectional size at a first location along the first semiconductor column is less than a second cross-sectional size at a second location along the first semiconductor column.

8. The semiconductor arrangement of claim 1, wherein the first semiconductor column comprises at least one of silicon or polysilicon.

9. The semiconductor arrangement of claim 1, comprising a gate electrode around at least some of the first semiconductor column.

10. A semiconductor arrangement comprising:

a substrate region;

a first semiconductor column projecting from the substrate region;

a second semiconductor column projecting from the substrate region, the second semiconductor column separated a first distance from the first semiconductor column along a first axis, the first distance between about 10 nm to about 30 nm; and

a third semiconductor column projecting from the substrate region, the third semiconductor column separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis, the second distance between about 10 nm to about 30 nm.

11. The semiconductor arrangement of claim 10, wherein a cross-section of the first semiconductor column is substantially circular.

12. The semiconductor arrangement of claim 10, comprising a fourth semiconductor column projecting from the substrate region, the fourth semiconductor column separated the first distance from the first semiconductor column.

13. The semiconductor arrangement of claim 12, the fourth semiconductor column separated the first distance from the first semiconductor column along the first axis.

14. The semiconductor arrangement of claim 10, comprising a fifth semiconductor column projecting from the substrate region, the fifth semiconductor column separated a second distance from the first semiconductor column along the second axis.

15. A method of forming a semiconductor arrangement, comprising:

forming a first mask region over a substrate region;

forming a second mask region over the first mask region;

patterning the first mask region and the second mask region; and

forming a first semiconductor column and a second semiconductor column from the substrate region under the first mask region, the second semiconductor column separated a first distance from the first semiconductor column, the first distance between about 10 nm to about 30 nm.

16. The method of claim 15, wherein the first mask region comprises a first mask portion and a second mask portion, the second mask region comprises a third mask portion and a fourth mask portion, the patterning comprising:

removing the fourth mask portion and fourth areas of the second mask portion under the fourth mask portion; and

removing the third mask portion and the first mask portion.

17. The method of claim 16, wherein the first semiconductor column and the second semiconductor column are formed under second areas of the second mask portion under the third mask portion.

18. The method of claim 15, wherein the first mask region comprises a first mask portion and a second mask portion, the second mask region comprises a third mask portion and a fourth mask portion, the patterning comprising:

removing the third mask portion and first areas of the first mask portion under the third mask portion; and

removing the fourth mask portion and the second mask portion.

19. The method of claim 18, wherein the first semiconductor column and the second semiconductor column are formed under third areas of the first mask portion under the fourth mask portion.

20. The method of claim 15, comprising forming a third semiconductor column from the substrate region under the first mask region, the third semiconductor column separated a second distance from the first semiconductor column, the second distance between about 10 nm to about 30 nm.