SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR COLUMNS

• US 20150048442A1
• Filed: 05/26/2014
• Published: 02/19/2015
• Est. Priority Date: 08/16/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Wang, Chih-Hao, Guo, Ta-Pen, Dian, Carlos H.
• Granted Patent: US 9,764,950 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.

Claims

1. A semiconductor arrangement comprising:

a substrate region;

a first semiconductor column projecting from the substrate region; and

a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column, the second semiconductor column separated a first distance from the first semiconductor column along a first axis; and

a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column, the third semiconductor column separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis, the second distance different than the first distance.

2. The semiconductor arrangement of claim 1, wherein the first distance is less than the second distance.

3. The semiconductor arrangement of claim 1, wherein the first distance is between about 10 nm to about 30 nm.

4. The semiconductor arrangement of claim 1, wherein the second distance is between about 30 nm to about 50 nm.

5. The semiconductor arrangement of claim 1, comprising a fourth semiconductor column projecting from the substrate region.

6. The semiconductor arrangement of claim 5, wherein the fourth semiconductor column is adjacent the second semiconductor column.

7. The semiconductor arrangement of claim 6, wherein the fourth semiconductor column is separated the second distance from the second semiconductor column along a third axis that is substantially perpendicular to the first axis.

8. The semiconductor arrangement of claim 5, wherein the fourth semiconductor column is adjacent the third semiconductor column.

9. The semiconductor arrangement of claim 8, wherein the fourth semiconductor column is separated the first distance from the third semiconductor column along a fourth axis that is substantially perpendicular to the second axis.

10. The semiconductor arrangement of claim 1, comprising a fourth semiconductor column projecting from the substrate region, wherein the fourth semiconductor column is:

adjacent the second semiconductor column,

separated the second distance from the second semiconductor column along a third axis that is substantially perpendicular to the first axis,

adjacent the third semiconductor column, and

separated the first distance from the third semiconductor column along a fourth axis that is substantially perpendicular to the second axis, wherein the first semiconductor column, the second semiconductor column, the third semiconductor column and the fourth semiconductor column are disposed within an area defined by the first distance times the second distance.

11. The semiconductor arrangement of claim 10, wherein the area is between about 500 nm² to about 700 nm².

12. The semiconductor arrangement of claim 1, wherein a first cross-section of the first semiconductor column is substantially circular.

13. The semiconductor arrangement of claim 1, wherein a second cross-section of the second semiconductor column is substantially circular.

14. The semiconductor arrangement of claim 1, wherein a third cross-section of the third semiconductor column is substantially circular.

15. A semiconductor arrangement comprising:

a substrate region;

a first semiconductor column projecting from the substrate region;

a second semiconductor column projecting from the substrate region, the second semiconductor column separated a first distance from the first semiconductor column along a first axis, the first distance between about 10 nm to about 30 nm; and

a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column, the third semiconductor column separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis, the second distance between about 30 nm to about 50 nm.

16. The semiconductor arrangement of claim 15, comprising a fourth semiconductor column projecting from the substrate region, wherein the fourth semiconductor column is:

adjacent the second semiconductor column along a third axis that is substantially perpendicular to the first axis, and

adjacent the third semiconductor column along a fourth axis that is substantially perpendicular to the second axis.

17. The semiconductor arrangement of claim 16, wherein the fourth semiconductor column is:

separated the second distance from the second semiconductor column, and

separated the first distance from the third semiconductor column.

18. A method of forming a semiconductor arrangement, comprising:

forming a first mask region over a substrate region;

forming a second mask region over the first mask region;

patterning the first mask region and the second mask region to form a first patterned mask region; and

using the first patterned mask region to form a first semiconductor column, a second semiconductor column, and a third semiconductor column from the substrate region, the second semiconductor column adjacent the first semiconductor column and separated a first distance from the first semiconductor column along a first axis, the third semiconductor column adjacent the first semiconductor column and separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis, the second distance different than the first distance.

19. The method of claim 18, wherein the first mask region comprises a first mask portion and a second mask portion, and the second mask region comprises a third mask portion and a fourth mask portion, the patterning comprising:

removing the fourth mask portion and fourth areas of the second mask portion under the fourth mask portion; and

removing the third mask portion and the first mask portion such that the first semiconductor column, the second semiconductor column, and the third semiconductor column are formed under second areas of the second mask portion under the third mask portion.

20. The method of claim 19, comprising forming a fourth semiconductor column from the substrate region under the second areas of the second mask portion, the fourth semiconductor column:

adjacent the second semiconductor column along a third axis that is substantially perpendicular to the first axis, and

adjacent the third semiconductor column along a fourth axis that is substantially perpendicular to the second axis.