CMOS COMPATIBLE WAFER BONDING LAYER AND PROCESS

• US 20150048509A1
• Filed: 08/14/2014
• Published: 02/19/2015
• Est. Priority Date: 08/16/2013
• Status: Abandoned Application

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: TIAN, Jingze, YELEHANKA, Pradeep Ramachandramurthy, KUMAR, Rakesh, NAGARAJAN, Ranganathan, TAN, Fu Chuen, LOW, Kia Hwee Samuel, YIK, Chun Hoe, WU, Jiaqi
• Application Number:
  US14/459,329
• Publication Number:
  US 20150048509A1
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/033 Thermal bonding
• CPC Class Codes: B81C 2203/0785 Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/185 Joining of semiconductor bodies for junction formation
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05681 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/2908 being stacked
• CPC Class Codes: H01L 2224/29124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32502 : comprising an eutectic alloy
• CPC Class Codes: H01L 2224/85805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 23/4827 : Materials
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/26 : Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN

Abstract

A wafer bonding layer and a process for using the same for bonding wafers are presented. The wafer bonding process includes providing a first wafer, providing a second type wafer and providing a water bonding layer. The wafer bonding layer is provided separately on a contact surface layer of the first or second wafer as part of a CMOS compatible processing recipe.

Claims

1. A wafer bonding process comprising:

providing a first wafer,

providing a second wafer; and

providing a wafer bonding layer, wherein the wafer bonding layer is provided separately on a contact surface layer of the first or second wafer as part of a CMOS compatible processing recipe.

2. The wafer bonding process of claim 1 wherein the wafer bonding layer is provided on the contact surface layer of the second wafer and the contact surface layer of the first wafer is an Aluminum layer.

3. The wafer bonding process of claim 1 wherein the wafer bonding layer comprises a bonding layer which is a CMOS foundry compatible material which forms a eutectic bond with an Aluminum contact surface layer of the first or second wafer.

4. The wafer bonding process of claim 1 wherein the wafer bonding layer comprises at least a Ge layer.

5. The wafer bonding process of claim 1 wherein the wafer bonding layer comprises a Ge layer and a barrier layer.

6. The wafer bonding process of claim 5 wherein the barrier layer comprises Ti, TiN, Ta, TaN or alloys thereof.

7. The wafer bonding process of claim 5 wherein the Ge layer has a thickness of about 0.2-0.6 μ

m and barrier layer is preferably about 0.1-0.3 μ

m.

8. The wafer bonding process of claim 1 wherein the first and second wafers comprise wafers of the same type.

9. The wafer bonding process of claim 1 wherein the first and second wafers comprise a CMOS wafer.

10. The wafer bonding process of claim 1 wherein the first wafer comprises a CMOS wafer and the second wafer comprise a MEMS wafer.

11. A wafer bonding layer comprising:

a Ge layer over a barrier layer, wherein the harrier layer may be an electrical conductor or an electrical insulator.

12. The wafer bonding layer of claim 11 wherein the barrier layer is an electrical conductor and comprises Ti, TiN, Ta, TaN or alloys thereof and has a thickness of about 0.1-0.3 μ

m.

13. The wafer bonding layer of claim 11 wherein the barrier layer is an electrical insulator comprising amorphous silicon having a thickness of about 0.2-1.0 μ

m.

14. The wafer bonding layer of claim 11 wherein the Ge layer comprises a Ge/Al multilayer that includes a series of thinner Ge layers that is interspersed in an alternating manner with a series of thinner Al layers.

15. The wafer bonding layer claim 14 wherein the thinner Ge and Al layers each having a thickness of about 0.1-0.2 μ

m.

16. A wafer bonding process comprising:

providing a first wafer,

providing a second wafer; and

providing a wafer bonding layer, wherein the wafer bonding layer is provided separately on a contact surface layer of the first or second wafer as part of a CMOS compatible processing recipe, wherein the contact surface layer of the other wafer is an Aluminum layer.

17. The wafer bonding process of claim 16 wherein the wafer bonding layer comprises a Ge/Al multilayer that includes a series of thinner Ge layers that is interspersed in an alternating manner with a series of thinner Al layers.

18. The wafer bonding process of claim 17 wherein the wafer bonding layer comprises the Ge/Al multilayer and a barrier layer.

19. The wafer bonding process of claim 17 wherein the wafer bonding layer comprises the Ge/Al multilayer and an amorphous silicon layer.

20. The wafer bonding process of claim 17 wherein the first wafer comprises a CMOS wafer and the second wafer comprise a MEMS wafer.