MAGNETIC CONTACTS

• US 20150048520A1
• Filed: 08/13/2013
• Published: 02/19/2015
• Est. Priority Date: 08/13/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Skinner, Michael P., Albers, Sven, Seidemann, Georg, Ossiander, Teodora
• Granted Patent: US 9,142,475 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01F 7/04 Means for releasing the attractive force
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/11332 using a powder
• CPC Class Codes: H01L 2224/11522 Auxiliary means therefor, e.g. for self-assembly activation
• CPC Class Codes: H01L 2224/132 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13298 Fillers
• CPC Class Codes: H01L 2224/13355 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13357 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/1336 Iron [Fe] as principal constituent
• CPC Class Codes: H01L 2224/13444 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13464 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13469 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/1601 Structure
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/811 the bump connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/81139 Guiding structures on the body
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/32 : Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49866 : characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Claims

1. An apparatus comprising:

a first integrated circuit (IC) substrate having a first electrical routing feature and a first magnet coupled with the first electrical routing feature;

a second integrated circuit (IC) substrate having a second electrical routing feature and a second magnet coupled with the second electrical routing feature; and

an interconnect structure coupled with the first and second electrical routing features, the interconnect structure comprising a plurality of magnetic particles, wherein the first magnet and the second magnet are configured to generate a magnetic field between the first magnet and the second magnet and wherein the magnetic particles are electrically conductive and disposed in the magnetic field.

2. The apparatus of claim 1, wherein the magnetic particles are movably coupled together and the interconnect structure is pliable.

3. The apparatus of claim 1, wherein the magnetic particles have an electrically conductive outer portion and a magnetic interior portion.

4. The apparatus of claim 1, wherein the first magnet is embedded in the first integrated circuit substrate.

5. The apparatus of claim 1, wherein the first magnet is disposed within the first electrical routing feature.

6. The apparatus of claim 5, wherein:

the first electrical routing feature comprises a first pillar having a base portion adjacent to the first IC substrate and a top portion distal to the first IC substrate; and

the second electrical routing feature comprises a second pillar having a base portion adjacent to the second IC substrate and a top portion distal to the second IC substrate.

7. The apparatus of claim 6, wherein:

the first magnet is disposed within the base portion of the first pillar; and

the second magnet is disposed within the base portion of the second pillar.

8. The apparatus of claim 6, wherein:

the first magnet is disposed within the top portion of the first pillar; and

the second magnet is disposed within the top portion of the second pillar.

9. The apparatus of claim 6, wherein:

the first magnet extends in a first lengthwise dimension from the base portion of the first pillar to the top portion of the first pillar;

the second magnet extends in a second lengthwise dimension from the base portion of the second pillar to the top portion of the second pillar;

the first lengthwise dimension is a largest dimension of the first magnet; and

the second lengthwise dimension is a largest dimension of the second magnet.

10. The apparatus of claim 9, wherein:

the first IC substrate has a third electrical routing feature comprising a third pillar, a third magnet in the third pillar, and a fourth magnet disposed in the first IC substrate; and

the fourth magnet is magnetically coupled with the first magnet and the third magnet.

11. The apparatus of claim 1, wherein the first integrated circuit substrate includes a die.

12. The apparatus of claim 11, wherein the second integrated circuit substrate includes another die, an interposer, or a package substrate.

13. The apparatus of claim 1, further comprising a spacer disposed between the first and second integrated circuit substrates, wherein the spacer is configured to maintain a minimum distance between the first and second integrated circuit substrates.

14. The apparatus of claim 1, wherein the first and second electrical routing features are spaced apart by a gap, and the plurality of magnetic particles forms a conductive bridge across the gap from the first electrical routing feature to the second electrical routing feature.

16. The apparatus of claim 1, wherein the first electrical routing feature includes a plurality of first electrical routing features, and the first magnet includes a plurality of first magnets coupled with corresponding ones of the plurality of first electrical routing features, and wherein the first magnets are arranged to form a checkerboard pole orientation pattern.

17. The apparatus of claim 1, wherein the first electrical routing feature includes a plurality of first electrical routing features, and the first magnet includes a plurality of first magnets coupled with corresponding ones of the plurality of first electrical routing features, and wherein the first magnets are arranged to form an alternating row pole orientation pattern.

15. The apparatus of claim 15, wherein the gap has a height and the magnetic particles have an average diameter in the range of 0.1% to 10% of the height of the gap.

18. A method, comprising:

generating a magnetic field between a first electrical routing feature of a first integrated circuit substrate and a second electrical routing feature of a second integrated circuit substrate, wherein the magnetic field extends across a gap between the first and second electrical routing features; and

forming an interconnect structure between the first and second electrical routing features, wherein the interconnect structure comprises a plurality of conductive magnetic particles.

19. The method of claim 18, wherein one or more of the first integrated circuit substrate and the second integrated circuit substrate includes a die.

20. The method of claim 19, wherein generating the magnetic field includes embedding a first magnet into the first electrical routing feature or the first integrated circuit substrate, and embedding a second magnet into the second electrical routing feature or the second integrated circuit substrate.

21. The method of claim 20, wherein generating the magnetic field includes positioning the first and second electrical routing features in substantial proximity such that corresponding first and second magnetic fields of the first and second magnets overlap along said gap.

22. The method of claim 18, wherein forming the interconnect structure between the first and second electrical routing features includes applying the plurality of conductive magnetic particles to one or more of the first and second integrated circuit substrates.

23. The method of claim 18, wherein forming the interconnect structure between the first and second electrical routing features includes dispensing the plurality of conductive magnetic particles into a gap between the first and second integrated circuit substrates.

24. A method comprising:

reducing a magnetic field between a first electrical routing feature of a first integrated circuit substrate and a second electrical routing feature of a second integrated circuit substrate, wherein a plurality of conductive magnetic particles are disposed in a gap between the first and second electrical routing features and reducing the magnetic field reduces a magnetic attraction between the conductive magnetic particles and the first and second electrical routing features; and

separating the first integrated circuit substrate from the second integrated circuit substrate.

25. The method of claim 24, wherein the first and second integrated circuit substrates include one or more magnets coupled with the first and second electrical routing features, and reducing the magnetic field includes heating the one or more magnets to a Curie temperature of the one or more magnets.

26. A system comprising:

a circuit board; and

a package assembly coupled with the circuit board, the package assembly including

a first integrated circuit substrate having a first electrical routing feature and a first magnet coupled with the first electrical routing feature,

a second integrated circuit substrate having a second electrical routing feature and a second magnet coupled with the second electrical routing feature, and

an interconnect structure coupled with the first and second electrical routing features, the interconnect structure comprising a plurality of magnetic particles, wherein the magnetic particles are electrically conductive.

27. The system of claim 26, wherein the magnetic particles are movably coupled together and the interconnect structure is pliable.

28. The system of claim 26, wherein the first electrical routing feature includes a plurality of first electrical routing features, and the first magnet includes a plurality of first magnets coupled with corresponding ones of the plurality of first electrical routing features, and wherein the first magnets are arranged to form a checkerboard pole orientation pattern.

29. The system of claim 26, wherein the first electrical routing feature includes a plurality of first electrical routing features, and the first magnet includes a plurality of first magnets coupled with corresponding ones of the plurality of first electrical routing features, and wherein the first magnets are arranged to form an alternating row pole orientation pattern.