RETRIEVAL HASH INDEX

• US 20150052286A1
• Filed: 08/15/2013
• Published: 02/19/2015
• Est. Priority Date: 08/15/2013
• Status: Active Grant

• Current Assignee: Ampere Computing LLC
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Svendsen, Kjeld
• Granted Patent: US 9,367,454 B2
• Time in Patent Office: Days
• US Class Current: 711/3
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

Claims

1. A device configured for managing cache memory addressing, comprising:

a memory controller component configured for receiving data comprising an address that comprises tag data representing a first memory location and index data representing a second memory location;

an addressing component configured for generating a hash index that defines a logical identity between the tag data and the index data; and

a tag memory component configured for storing at least one entry comprising the hash index.

2. The device of claim 1, wherein the tag memory component is further configured for, in response to the addressing component generating the hash index, dropping the index data.

3. The device of claim 1, wherein the addressing component is further configured for recovering the index data as a function of the hash index and the tag data.

4. The device of claim 2, wherein the memory controller component is configured for evicting an entry from a data memory component of the cache based on the recovered index data.

5. The device of claim 1, wherein the addressing component is further configured for generating the hash index as an exclusive—

or identity based on the tag data and the index data.

6. The device of claim 1, wherein the tag memory component is further configured for storing the tag data.

7. The device of claim 1, wherein the memory controller component is further configured for instructing the tag memory component to evict an entry of the at least one entry.

8. The device of claim 1, wherein the memory controller component is further configured for instructing the tag memory component to evict the entry based on a predetermined criterion.

9. The device of claim 1, wherein the addressing component is further configured for generating compressed tag data based on the tag data and a predefined hash function.

10. A method of managing cache addressing of a system, comprising:

receiving data comprising an address that comprises tag data representing a first memory location and index data representing a second memory location;

generating a hash index that defines a logical relationship between the tag data and the index data; and

storing at least one entry comprising the hash index while releasing the index data.

11. The method of claim 10, further comprising recovering a value of the index data based on the hash index and the tag data

12. The method of claim 11, further comprising recovering the value of the index data by performing an exclusive—

or operation on the tag data and the hash index.

13. The method of claim 11, further comprising evicting an entry from the system based on the recovered value of the index data.

14. The method of claim 10, further comprising compressing the tag data based on a predefined compressing function.

15. The method of claim 14, wherein the generating the hash index is based on the compressed tag data and the index data.

16. A system for cache miss detection comprising:

means for receiving at least one of request;

means for determining an address associated with the at least one request, wherein the address comprises tag data and index data;

means for generating an identity defining a relationship between the tag data and the index data; and

means for storing the tag data and the identity, and dropping the index data.

17. The system of claim 16 further comprising:

means for hashing the tag data.

18. The system of claim 17 further comprising:

means for generating the identity as a bitwise exclusive—

or relationship between the hashed tag data and the index data.

19. The system of claim 18 further comprising means for generating data identical to the index data based on the identity and the index data.

20. The system of claim 19 further comprising means for evicting stored data as a function of the generated data.