MANAGEMENT OF TRANSACTIONAL MEMORY ACCESS REQUESTS BY A CACHE MEMORY
7 Assignments
0 Petitions
Accused Products
Abstract
In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.
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Citations
20 Claims
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1-6. -6. (canceled)
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7. A processing unit for a data processing system including a shared memory system, the processing unit comprising:
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a processor core; and a cache memory coupled to the processor core, the cache memory including; a cache array; a directory; read-claim logic that service memory access requests of the processor core; and dispatch logic that, responsive to receiving a transactional memory access request issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core, evaluates the transactional memory access request for dispatch by determining whether the memory transaction has a failing transaction state, and wherein the dispatch logic, responsive to determining the memory transaction has a failing transaction state, refrains from dispatching the memory access request for service by the read-claim logic and refrains from updating at least replacement order information in the directory in response to the transactional memory access request. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A design structure tangibly embodied in a machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a processing unit for a data processing system including a shared memory system, the processing unit including; a processor core; and a cache memory coupled to the processor core, the cache memory including; a cache array; a directory; read-claim logic that service memory access requests of the processor core; and dispatch logic that, responsive to receiving a transactional memory access request issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core, evaluates the transactional memory access request for dispatch by determining whether the memory transaction has a failing transaction state, and wherein the dispatch logic, responsive to determining the memory transaction has a failing transaction state, refrains from dispatching the memory access request for service by the read-claim logic and refrains from updating at least replacement order information in the directory in response to the transactional memory access request. - View Dependent Claims (15, 16, 17, 18, 19, 20)
Specification