Determining Data Retention Time in a Solid-State Non-Volatile Memory

• US 20150052416A1
• Filed: 08/16/2013
• Published: 02/19/2015
• Est. Priority Date: 08/16/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Prohofsky, Thomas R., Johnston, Darren E.
• Granted Patent: US 9,263,158 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes

Abstract

Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time.

Claims

1. A method comprising

writing a test pattern to a selected block of solid-state non-volatile memory cells;

reading the test pattern from the selected block and identifying a total number of read errors;

determining a data retention time responsive to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern; and

refreshing data in a second block of the solid-state non-volatile memory cells responsive to the determined data retention time.

2. The method of claim 1, further comprising communicating the determined data retention time to a host device.

3. The method of claim 1, further comprising allocating the selected block from a pool of blocks available for allocation for storage of user data prior to the writing of the test pattern thereto, and returning the selected block to the pool of blocks available for allocation for storage of user data after the determining of the data retention time.

4. The method of claim 1, wherein the selected block comprises a garbage collection unit (GCU) comprising a plurality of erasure blocks of memory cells each of which are erased as a unit.

5. The method of claim 1, wherein the solid-state non-volatile memory cells comprises flash memory cells and the selected block comprises at least one erasure block of said flash memory cells.

6. The method of claim 1, wherein the total number of read errors is identified by applying an error correction code (ECC) to detect and correct at least one error in the readback data.

7. The method of claim 1, wherein the total number of read errors is identified by comparing the test pattern read back from the selected block with an original copy of the test pattern.

8. The method of claim 1, wherein the refreshing data comprises identifying sets of user data stored in the array having a total storage time greater than or equal to the determined retention time, and copying the identified sets to a new location in the memory.

9. The method of claim 1, wherein the data retention time comprises an estimated time during which the memory can store a set of data in a powered down condition and can successfully retrieve the data after being subsequently powered up.

10. The method of claim 9, wherein the data retention time is correlated to a specified temperature of the memory while the memory is in the powered down condition.

11. An apparatus comprising:

an array of solid-state non-volatile memory cells arranged into addressable blocks;

an evaluation circuit adapted to write a test pattern to a selected block, subsequently read the test pattern from the selected block, identify a total number of read errors in the subsequently read test pattern, and determine a data retention time responsive to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern; and

a controller adapted to refresh data in a second block of the solid-state non-volatile memory cells responsive to the determined data retention time.

12. The apparatus of claim 11 characterized as a data storage device coupled to a host device, wherein the controller communicates the determined data retention time to the host device.

13. The apparatus of claim 11, wherein the evaluation circuit allocates the selected block from a pool of blocks available for allocation for storage of user data prior to the writing of the test pattern thereto, and returns the selected block to the pool of blocks available for allocation for storage of user data after the determining of the data retention time.

14. The apparatus of claim 11, wherein the selected block comprises a garbage collection unit (GCU) comprising a plurality of erasure blocks of memory cells each of which are erased as a unit.

15. The apparatus of claim 11, wherein the solid-state non-volatile memory cells comprises flash memory cells and the selected block comprises at least one erasure block of said flash memory cells.

16. The apparatus of claim 11, wherein the total number of read errors is identified by applying an error correction code (ECC) to detect and correct at least one error in the readback data.

17. The apparatus of claim 11, wherein the total number of read errors is identified by comparing the test pattern read back from the selected block with an original copy of the test pattern.

18. An apparatus comprising:

a flash memory array arranged into a plurality of garbage collection units (GCUs) erased and allocated as a unit;

an evaluation circuit which determines a current data retention time of the flash memory array by storing a test pattern in a selected GCU and, at the conclusion of an elapsed time interval, identifies a total number of errors in a copy of the test pattern read back from the selected GCU; and

a controller which communicates the current data retention time to a host device.

19. The apparatus of claim 18, wherein the controller further operates to move a set of data from a second GCU to a third GCU of the flash memory array responsive to the set of data being stored in the second GCU for a period of time equal to or greater than the current data retention time.

20. The apparatus of claim 18, wherein the current data retention time comprises an elapsed period of time during which the flash memory array can store a set of data without an application of power to the array and return the set of data after being powered up at the conclusion of the elapsed period of time.