SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20150053977A1
• Filed: 10/20/2014
• Published: 02/26/2015
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 9,780,225 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device capable of high speed operation is provided. Further, a semiconductor device in which change in electric characteristics due to a short channel effect is hardly caused is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed by self-aligned process in which one or more elements selected from Group 15 elements are added to the semiconductor layer with the use of a gate electrode as a mask. The source region and the drain region can have a wurtzite crystal structure.

Claims

1. (canceled)

2. A semiconductor device comprising:

an oxide semiconductor layer including a channel formation region, a source region and a drain region,

wherein;

the oxide semiconductor layer contains zinc, indium and gallium;

the channel formation region includes crystals;

the crystals are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer;

the crystals comprise atoms arranged to have a triangular or hexagonal shape in an a-b plane;

each of the source region and the drain region includes at least one element selected from Group 15 elements; and

the source region and the drain region have a wurtzite crystal structure.

3. The semiconductor device according to claim 2, wherein:

a concentration of the at least one element selected from Group 15 elements included in the source region is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³; and

a concentration of the at least one element selected from Group 15 elements included in the drain region is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

4. The semiconductor device according to claim 2, wherein the at least one element is nitrogen.

5. The semiconductor device according to claim 2, further comprising an insulating layer under the oxide semiconductor layer, wherein:

an amount of oxygen released from the insulating layer is greater than or equal to 3.0×

10²⁰ atoms/cm³ in thermal desorption spectroscopy when the amount of oxygen is converted into oxygen atoms;

the insulating layer contains oxygen and is capable of supplying oxygen to the oxide semiconductor layer; and

the insulating layer contains SiO_x where x is larger than 2.

6. The semiconductor device according to claim 2, further comprising a gate electrode over the oxide semiconductor layer, wherein the source region and the drain region are formed by self-aligned process with respect to the gate electrode.

7. A semiconductor device comprising:

an oxide semiconductor layer including a channel formation region, a source region and a drain region,

wherein;

the channel formation region includes crystals;

the crystals are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer;

the crystals comprise atoms arranged to have a triangular or hexagonal shape in an a-b plane;

an energy gap of the channel formation region is larger than an energy gap of each of the source region and the drain region; and

the energy gap of the channel formation region is 2.5 eV or more.

8. The semiconductor device according to claim 7, wherein:

each of the source region and the drain region includes at least one element selected from Group 15 elements;

a concentration of the at least one element selected from Group 15 elements included in the source region is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³; and

a concentration of the at least one element selected from Group 15 elements included in the drain region is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

9. The semiconductor device according to claim 8, wherein the at least one element is nitrogen.

10. The semiconductor device according to claim 7, further comprising an insulating layer under the oxide semiconductor layer, wherein:

an amount of oxygen released from the insulating layer is greater than or equal to 3.0×

10²⁰ atoms/cm³ in thermal desorption spectroscopy when the amount of oxygen is converted into oxygen atoms;

the insulating layer contains oxygen and is capable of supplying oxygen to the oxide semiconductor layer; and

the insulating layer contains SiO_x where x is larger than 2.

11. The semiconductor device according to claim 7, further comprising a gate electrode over the oxide semiconductor layer, wherein the source region and the drain region are formed by self-aligned process with respect to the gate electrode.

12. The semiconductor device according to claim 7, further comprising a source electrode electrically connected to the source region, wherein:

a work function of the channel formation region is larger than a work function of the source region; and

the work function of the source region is larger than a work function of the source electrode.

13. The semiconductor device according to claim 7, wherein the energy gap of the channel formation region is 3 eV or more.

14. A semiconductor device comprising:

an oxide semiconductor layer including a channel formation region, a source region and a drain region,

wherein;

the oxide semiconductor layer contains zinc, indium and gallium;

the channel formation region includes crystals;

the crystals are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer;

the crystals comprise atoms arranged to have a triangular or hexagonal shape in an a-b plane;

each of the source region and the drain region includes at least one element selected from Group 15 elements;

the source region and the drain region have a wurtzite crystal structure;

an energy gap of the channel formation region is larger than an energy gap of each of the source region and the drain region; and

the energy gap of the channel formation region is 2.5 eV or more.

15. The semiconductor device according to claim 14, wherein:

a concentration of the at least one element selected from Group 15 elements included in the source region is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³; and

a concentration of the at least one element selected from Group 15 elements included in the drain region is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

16. The semiconductor device according to claim 14, wherein the at least one element is nitrogen.

17. The semiconductor device according to claim 14, further comprising an insulating layer under the oxide semiconductor layer, wherein:

an amount of oxygen released from the insulating layer is greater than or equal to 3.0×

10²⁰ atoms/cm³ in thermal desorption spectroscopy when the amount of oxygen is converted into oxygen atoms;

the insulating layer contains oxygen and is capable of supplying oxygen to the oxide semiconductor layer; and

the insulating layer contains SiO_x where x is larger than 2.

18. The semiconductor device according to claim 14, further comprising a gate electrode over the oxide semiconductor layer, wherein the source region and the drain region are formed by self-aligned process with respect to the gate electrode.

19. The semiconductor device according to claim 14, further comprising a source electrode electrically connected to the source region, wherein:

a work function of the channel formation region is larger than a work function of the source region; and

the work function of the source region is larger than a work function of the source electrode.

20. The semiconductor device according to claim 14, wherein the energy gap of the channel formation region is 3 eV or more.