3D MEMORY ARRAY WITH IMPROVED SSL AND BL CONTACT LAYOUT

• US 20150054057A1
• Filed: 10/14/2014
• Published: 02/26/2015
• Est. Priority Date: 07/06/2010
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hung, Chun Hsiung, Lue, Hang-Ting, Shen, Shin-Jang
• Granted Patent: US 9,024,374 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays

Abstract

A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.

Claims

1. A memory device, comprising:

an integrated circuit substrate;

a plurality of stacks of semiconductor material strips extending out of the integrated circuit substrate, the plurality of stacks including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions, the semiconductor material strips that share a same plane position of the plurality of plane positions being interconnected;

a first plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the semiconductor material strips and the first plurality of conductive lines; and

memory elements in the interface regions, which establish a 3D array of memory cells accessible via the semiconductor material strips and the first plurality of conductive lines;

a plurality of conductive conformal structures, each conductive conformal structure of the plurality of conductive conformal structures over a different stack of the plurality of stacks;

a second plurality of conductive lines arranged over the plurality of stacks, and parallel to the semiconductor material strips, each conductive line of the second plurality of conductive lines electrically connected to a different conductive conformal structure of the plurality of conductive conformal structures; and

a third plurality of conductive lines arranged over, and parallel to, the first plurality of conductive lines, each conductive line of the third plurality of conductive lines connected to a different conductive line of the second plurality of conductive lines.

2. The memory device of claim 1, including

decoding circuits coupled, for accessing the memory cells, to the semiconductor material strips in the plurality of stacks, the first plurality of conductive lines, and the third plurality of conductive lines.

3. The memory device of claim 1, wherein the memory elements comprise an anti-fuse.

4. The memory device of claim 1, wherein the memory elements comprise a charge storage structure.

5. The memory device of claim 1, wherein the memory cells comprise buried channel charge storage transistors.

6. The memory device of claim 1, wherein the plurality semiconductor material strips in the stacks comprise a doped semiconductor.

7. The memory device of claim 1, wherein the first plurality of conductive lines comprise a doped semiconductor.

8. The memory device of claim 1, wherein said memory elements comprise portions of a common layer of memory material between the first plurality of conductive lines and the plurality of stacks.

9. The memory device of claim 1, including a tunneling layer, a charge trapping layer and a blocking layer between the first plurality of conductive lines and the plurality of stacks, and wherein said tunneling layer, charge trapping layer and blocking layer, in combination, form said memory elements in said interface regions.

10. The memory device of claim 1, including a plurality of bit lines arranged over the plurality of stacks, and parallel to the semiconductor material strips, wherein different bit lines of the plurality of bit lines are electrically connected via a plurality of bit line contacts to different plane positions of the plurality of stacks.

11. A method for manufacturing a memory device, comprising:

forming a plurality of stacks of semiconductor material strips extending out of the integrated circuit substrate, the plurality of stacks including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions, the semiconductor material strips that share a same plane position of the plurality of plane positions being interconnected;

forming a first plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the semiconductor material strips and the first plurality of conductive lines; and

forming memory elements in the interface regions, which establish a 3D array of memory cells accessible via the semiconductor material strips and the first plurality of conductive lines;

forming a plurality of conductive conformal structures, each conductive conformal structure of the plurality of conductive conformal structures over a different stack of the plurality of stacks;

forming a second plurality of conductive lines arranged over the plurality of stacks, and parallel to the semiconductor material strips, each conductive line of the second plurality of conductive lines electrically connected to a different conductive conformal structure of the plurality of conductive conformal structures; and

forming a third plurality of conductive lines arranged over, and parallel to, the first plurality of conductive lines, each conductive line of the third plurality of conductive lines connected to a different conductive line of the second plurality of conductive lines.