NOVEL 3D STRUCTURE FOR ADVANCED SRAM DESIGN TO AVOID HALF-SELECTED ISSUE
First Claim
1. A static random access memory (SRAM) device comprising:
- a plurality of memory array layers vertically disposed one above another, each memory array layer comprising a plurality of memory cells and a word line disposed thereon, each word line being connected to the plurality of memory cells disposed on its memory array layer, wherein the number of memory cells in a layer corresponds to a predetermined memory page size;
a layer decoder circuit disposed on each memory array layer, each layer decoder circuit being configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer;
a word line driver circuit disposed on each memory array layer, each word line driver circuit being configured to drive the word line disposed on its memory array layer; and
a plurality of complementary bit line pairs, each complementary bit line pair extending vertically to couple a memory cell in each memory array layer.
1 Assignment
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Accused Products
Abstract
Disclosed is a novel static random access memory (SRAM) device. The SRAM device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs wherein each complementary bit line pair extends vertically to couple a memory cell in each memory array layer. Each memory array layer comprises a plurality of memory cells and a word line disposed thereon. Each word line is connected to the plurality of memory cells disposed on its memory array layer. The number of memory cells in a layer corresponds to a predetermined memory page size. Each layer decoder circuit is configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer. Each word line driver circuit is configured to drive the word line disposed on its memory array layer.
10 Citations
20 Claims
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1. A static random access memory (SRAM) device comprising:
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a plurality of memory array layers vertically disposed one above another, each memory array layer comprising a plurality of memory cells and a word line disposed thereon, each word line being connected to the plurality of memory cells disposed on its memory array layer, wherein the number of memory cells in a layer corresponds to a predetermined memory page size; a layer decoder circuit disposed on each memory array layer, each layer decoder circuit being configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer; a word line driver circuit disposed on each memory array layer, each word line driver circuit being configured to drive the word line disposed on its memory array layer; and a plurality of complementary bit line pairs, each complementary bit line pair extending vertically to couple a memory cell in each memory array layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A static random access memory (SRAM) device comprising:
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a plurality of memory array layers vertically disposed one above another, each memory array layer comprising a plurality of memory cells and a word line disposed thereon, wherein each word line is connected to the plurality of the memory cells disposed on its memory array layer, wherein the number of memory cells in a layer corresponds to a predetermined memory page size; a layer decoder circuit on each memory array layer, each layer decoder circuit being configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer; a word line driver configured to drive the word line disposed on the selected memory array layer; and a plurality of complementary bit line pairs, each complementary bit line pair extending vertically to couple to a memory cell in each memory array layer; wherein the SRAM device is configured to activate only the word line connected to those memory cells selected by the SRAM address so that a read operation or a write operation does not result in a non-selected memory cell consuming unnecessary power. - View Dependent Claims (11, 12, 13, 14)
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15. A method in a static random access memory (SRAM) device comprising:
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providing a plurality of memory array layers vertically disposed one above another, each memory array layer comprising a plurality of memory cells disposed thereon, each memory array layer further comprising a layer decoder configured to decode a portion of an SRAM address to determine the memory array layer on which the memory cells addressed by the SRAM address are disposed; providing a word line on each memory array layer, wherein each word line is connected to each memory cell in the memory array layer on which the word line is disposed; and providing a plurality of complementary bit line pairs, each complementary bit line pair extending vertically to couple to a memory cell in each memory array layer; wherein each word line is connected to a number of memory cells equal to the number of input/output data lines in the device. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification