On-The-Fly Trimmable Sense Amplifier

• US 20150055424A1
• Filed: 03/15/2013
• Published: 02/26/2015
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Zhou, Yao, Qian, Xiaozhou
• Granted Patent: US 9,431,072 B2
• Time in Patent Office: Days
• US Class Current: 365/189.15
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A trimmable sense amplifier for use in a memory device is disclosed.

Claims

1. A method for trimming a sense amplifier, comprising:

coupling a first sense amplifier to a selected memory cell and a reference circuit during a read operation;

decoupling the first sense amplifier from the selected memory cell and the reference circuit during a trim operation of the first sense amplifier;

coupling the selected memory cell and the reference circuit to a second sense amplifier during the trim operation of the first sense amplifier;

wherein the trim operation comprises determining a current level to apply to the first sense amplifier to compensate for transistor mismatching.

2. The method of claim 1, wherein the selected memory cell is a split gate non-volatile memory cell.

3. The method of claim 2, wherein the selected memory cell can store one of two different values.

4. The method of claim 2, wherein the selected memory cell can store one of four different values.

5. The method of claim 1, wherein the first sense amplifier is coupled to the selected cell through a switch.

6. The method of claim 1, wherein the reference circuit comprises a reference memory cell.

7. The method of claim 1, wherein the determining step comprises:

coupling the first sense amplifier to a reference current generator and a compensation circuit;

drawing current from the first sense amplifier using the reference current generator;

identifying transistor mismatching by monitoring the output of the first sense amplifier; and

applying a current flow to a node within the first sense amplifier to compensate for the transistor mismatching.

8. The method of claim 7, wherein the selected memory cell is a split gate non-volatile memory cell.

9. The method of claim 8, wherein the selected memory cell can store one of two different values.

10. The method of claim 8, wherein the selected memory cell can store one of four different values.

11. The method of claim 7, wherein the first sense amplifier is coupled to the selected cell through a switch.

12. A memory device, comprising:

a first sense amplifier for coupling to a selected memory cell and a reference circuit;

a second sense amplifier for coupling to the selected memory cell and the reference circuit; and

a switch for switching the coupling of the selected memory cell and the reference circuit from the first sense amplifier to the second sense amplifier.

13. The memory device of claim 12, wherein the selected memory cell is a split gate non-volatile memory cell.

14. The memory device of claim 13, wherein the selected memory cell can store one of two different values.

15. The memory device of claim 13, wherein the selected memory cell can store one of four different values.

16. The memory device of claim 12, wherein the memory device is configured to perform a trim operation on the first sense amplifier when the second sense amplifier is coupled to the selected memory cell and the reference circuit

17. The memory device of claim 16, wherein the first sense amplifier is coupled to a reference current generator and a compensation circuit during the trim operation.

18. The memory device of claim 17, wherein the selected memory cell is a split gate non-volatile memory cell.

19. The memory device of claim 18, wherein the selected memory cell can store one of two different values.

20. The memory device of claim 18, wherein the selected memory cell can store one of four different values.

21. The memory device of claim 12, wherein the reference circuit comprises a reference memory cell.

22. A memory device, comprising:

a sense amplifier;

a mismatch compensation circuit coupled to the sense amplifier;

a reference current generator coupled to the sense amplifier; and

a controller coupled to the sense amplifier and the mismatch compensation circuit.

23. The memory device of claim 22, wherein the reference current generator is coupled to the sense amplifier through a switch.