METHODS AND APPARATUSES INCLUDING TRANSMITTER CIRCUITS

• US 20150055431A1
• Filed: 08/23/2013
• Published: 02/26/2015
• Est. Priority Date: 08/23/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lin, Feng
• Granted Patent: US 9,153,312 B2
• Time in Patent Office: Days
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: H04L 25/00 Baseband systems
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

Methods and apparatuses are disclosed for transmitter circuits. One example apparatus includes a pre-driver circuit configured to provide a transition control signal responsive to received data, and a main driver circuit configured to drive an output node responsive to the transition control signal. The apparatus also includes a feedback circuit configured to provide a feedback control signal responsive to a voltage of the output node reaching or exceeding a predefined threshold, and an equalizer driver circuit configured to assist the main driver circuit in driving the output node responsive to signals from at least one of the pre-driver circuit and the feedback circuit.

Claims

1. An apparatus, comprising:

a pre-driver circuit configured to provide a transition control signal responsive to received data;

a main driver circuit configured to drive an output node responsive to the transition control signal;

a feedback circuit configured to provide a feedback control signal responsive to a voltage of the output node reaching or exceeding a threshold; and

an equalizer driver circuit configured to assist the main driver circuit in driving the output node responsive to signals from at least one of the pre-driver circuit and the feedback circuit.

2. The apparatus of claim 1, wherein the main driver circuit being configured to drive an output node responsive to the transition control signal comprises the main driver circuit being configured to drive the output node responsive to the transition control signal and a feedback control signal, and wherein the equalizer driver circuit being configured to assist the main driver circuit in driving the output node responsive to signals from at least one of the pre-driver circuit and the feedback circuit comprises the equalizer driver circuit being configured to assist the main driver circuit in driving the output node responsive to signals from the pre-driver circuit and the feedback circuit.

3. The apparatus of claim 1, wherein the pre-driver circuit being configured to provide a transition control signal responsive to received data comprises the pre-driver circuit being configured to provide the transition control signal responsive to the received data and the feedback control signal.

4. The apparatus of claim 1, wherein the feedback control signal is a first feedback control signal, the equalizer driver circuit is configured to assist the main driver circuit in driving the output node responsive to a second feedback control signal.

5. The apparatus of claim 4, wherein the feedback circuit is configured to provide the second feedback control signal responsive to the first feedback control signal.

6. The apparatus of claim 4, wherein the feedback circuit is configured to invert the first feedback control signal in order to provide the second feedback control signal.

7. The apparatus of claim 1, wherein the main driver circuit is a small swing, ground-referenced driver circuit.

8. The apparatus of claim 1, wherein the equalizer driver circuit is configured to be enabled and disabled.

9. The apparatus of claim 8, wherein the transition control signal is a first transition control signal and the pre-driver circuit is configured to provide a second transition control signal to the equalizer driver circuit responsive to an equalizer enable signal.

10. The apparatus of claim 1, wherein the main driver circuit and the equalizer driver circuit together form a transmitter circuit of a first DRAM memory die, the apparatus further comprising a plurality additional DRAM memory dies and a controller die.

11. The apparatus of claim 10, wherein the transmitter is configured to transmit data from the first DRAM memory die to the controller die through a plurality of through silicon vias in respective additional DRAM memory dies, the equalizer driver circuit being configured to compensate for distortions of data transmitted to the controller die.

12. An apparatus, comprising:

a feedback circuit configured to provide first and second feedback control signals responsive to a voltage of a node;

a main driver circuit configured to drive the node based at least in part on the first feedback control signal; and

an equalizer circuit configured to provide additional current and/or voltage to the node during a data transition responsive to the second feedback control signal.

13. The apparatus of claim 12, wherein a drive strength of the equalizer circuit is no more than 20% of a drive strength of the main driver.

14. The apparatus of claim 12, wherein the equalizer circuit is configured to provide the additional current, voltage, or combinations thereof responsive to a transition control signal from a pre-driver circuit.

15. The apparatus of claim 12, wherein the equalizer circuit comprises a pull-up network and a pull-down network.

16. The apparatus of claim 15, wherein the pull-up network comprises a pFET and an nFET.

17. The apparatus of claim 15, wherein the pull-up network comprises a single pFET.

18. The apparatus of claim 17, wherein a pre-driver circuit is configured to provide a transition control signal to the feedback circuit, and the feedback circuit is further configured to provide the second feedback control signal responsive to the transition control signal.

19. A method, comprising:

providing output data to a channel using a main driver based on data received from an array;

providing a first feedback control signal to the main driver based on a voltage of an output node of the main driver; and

compensating for transmission effects in the channel using an equalizer circuit controlled at least in part by a second feedback control signal.

20. The method of claim 19, wherein the first and second feedback control signals are both provided by a feedback circuit coupled to the output node of the main driver.

21. The method of claim 19, wherein the equalizer circuit is further controlled by signals generated by a pre-driver circuit responsive to the data received from the array.

22. The method of claim 19, further comprising determining an edge of a data transition based at least in part on the second feedback control signal.

23. The method of claim 22, wherein the equalizer circuit is coupled to the output node of the main driver and the equalizer circuit compensates for high frequency losses in the channel by boosting transitions in the output data responsive to the determined edge of the data transition.

24. A method, comprising:

driving an output node responsive to input data using a main driver circuit; and

controlling an equalizer circuit responsive to a voltage of the output node, the equalizer circuit acting to assist the main driver circuit in driving the output node.

25. The method of claim 24, further comprising controlling the equalizer circuit responsive to the input data.

26. The method of claim 24, further comprising:

generating transition control signals using a pre-driver circuit; and

driving the output node using the main driver circuit responsive to the transition control signals.

27. The method of claim 26, further comprising controlling the equalizer circuit responsive to signals based on the transition control signals.

28. The method of claim 24, wherein the equalizer circuit is only active during transitions of the voltage of the output node.