Vertical Power MOSFET and Methods of Forming the Same

• US 20150056770A1
• Filed: 10/31/2014
• Published: 02/26/2015
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Liu, Ruey-Hsin, Su, Po-Chih
• Granted Patent: US 9,673,297 B2
• Time in Patent Office: Days
• US Class Current: 438/268
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.

Claims

1. A method comprising:

forming a gate dielectric layer over a body layer, wherein the body layer is over a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type;

forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space;

implanting a portion of the body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space;

forming a source region, wherein a portion of the source region overlaps the doped semiconductor region; and

forming a drain region underlying the semiconductor layer.

2. The method of claim 1, wherein the gate dielectric layer extends into the space, and the implanting is performed with an implanted impurity penetrating through a portion of the gate dielectric layer in the space.

3. The method of claim 1 further comprising:

implanting the body layer to form heavily doped regions on opposite sides of a combined region comprising the first gate electrode and the second gate electrode; and

etching portions of the body layer to expose sidewalls of the heavily doped regions.

4. The method of claim 3, wherein the heavily doped regions are of the first conductivity type.

5. The method of claim 3, wherein the source region comprises a metal, and the source region is in contact with the sidewalls of the heavily doped regions.

6. The method of claim 1, wherein the source region comprises a portion filled into the space, with the portion level with the first gate electrode and the second gate electrode.

7. The method of claim 1 further comprising:

before the forming the source region, forming a dielectric layer covering the first gate electrode and the second gate electrode;

forming a field plate over the dielectric layer; and

forming an inter-layer dielectric between the field plate and the source region.

8. The method of claim 7, wherein the field plate comprises a portion extending into the space and level with the first gate electrode and the second gate electrode.

9. The method of claim 1, wherein the doped semiconductor region penetrates through the body layer to contact the semiconductor layer.

10. A method comprising:

epitaxially growing an epitaxy semiconductor layer of a first conductivity type;

epitaxially growing a body layer over the epitaxy semiconductor layer, wherein the body layer is of a second conductivity type opposite the first conductivity type;

forming a gate dielectric layer over the body layer;

forming a first and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space;

implanting a portion of the body layer to form a doped semiconductor region of the first conductivity type, wherein the doped semiconductor region is overlapped by the space, and the doped semiconductor region extends to contact the epitaxy semiconductor layer;

forming a source region over the body layer; and

forming a drain region underlying the epitaxy semiconductor layer.

11. The method of claim 10, wherein the implanting the portion of the body layer is performed using the first and the second gate electrodes as a portion of an implantation mask.

12. The method of claim 10 further comprising forming a heavily doped semiconductor region of the first conductivity type, wherein the heavily doped semiconductor region and the doped semiconductor region are on opposite sides of a portion of the body layer that is overlapped by the first gate electrode.

13. The method of claim 10 further comprising:

after the doped semiconductor region is formed, forming a dielectric layer over the first and the second gate electrodes; and

etching the dielectric layer to form a contact opening, wherein a top surface of the body layer is exposed, and the source region comprises a first portion filled into the contact opening.

14. The method of claim 10 further comprising:

after the doped semiconductor region is formed, forming a dielectric layer over the first and the second gate electrodes; and

forming a conductive field plate over the dielectric layer, wherein the conductive field plate extends into the space between the first and the second gate electrodes.

15. The method of claim 10, wherein the doped semiconductor region is implanted to have an impurity concentration higher than an impurity concentration of the epitaxy semiconductor layer.

16. A method comprising:

forming a gate dielectric layer over a body layer, wherein the body layer is over a semiconductor layer, with the semiconductor layer being of a first conductivity type, and the body layer being of a second conductivity type opposite to the first conductivity type;

forming a first gate electrode and a second gate electrode over the gate dielectric layer, wherein the first and the second gate electrodes are spaced apart from each other by a space, with an intermediate portion of the gate dielectric layer being in the space;

implanting a portion of the body layer underlying the intermediate portion of the gate dielectric layer to form a doped semiconductor region of the first conductivity type;

forming a source region, wherein a portion of the source region overlaps the doped semiconductor region and the intermediate portion of the gate dielectric layer; and

forming a drain region underlying the semiconductor layer.

17. The method of claim 16, wherein in the implanting, the first gate electrode and the second gate electrode are used as a portion of an implantation mask.

18. The method of claim 16 further comprising:

implanting the body layer to form heavily doped regions on opposite sides of a combined region comprising the first gate electrode and the second gate electrode; and

etching portions of the body layer to expose sidewalls of the heavily doped regions.

19. The method of claim 18, wherein the source region comprises a metal, and the source region is in contact with the sidewalls of the heavily doped regions.

20. The method of claim 16, wherein the source region comprises a portion filled into the space, with the portion of the source region level with the first gate electrode and the second gate electrode.