METHOD TO MINIMIZE THE NUMBER OF IRQ LINES FROM PERIPHERALS TO ONE WIRE

• US 20150058507A1
• Filed: 08/18/2014
• Published: 02/26/2015
• Est. Priority Date: 08/24/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro, Wietfeldt, Richard Dominic, Wiley, George Alan
• Granted Patent: US 9,921,981 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 13/4226 with asynchronous protocol
• CPC Class Codes: G06F 2211/001 In-Line Device
• CPC Class Codes: G06F 2211/002 Bus

Abstract

A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

Claims

1. A master device, comprising:

a first interface to a single line interrupt request (IRQ) bus to which one or more slave devices are coupled;

a second interface to a control data bus to which the one or more slave devices are also coupled; and

a processing circuit coupled to the first interface and the second interface, the processing circuit adapted to;

group the one or more slave devices into one or more groups, where each group is associated with a different IRQ signal;

monitor the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device;

identify a group with which the IRQ signal is associated; and

scan the slave devices of the identified group to ascertain an asserting slave device which asserted the IRQ signal on the IRQ bus.

2. The device of claim 1, wherein the processing circuit is further adapted to:

grant the asserting slave device access to transmit data over the control data bus.

3. The device of claim 1, wherein the IRQ signal associated with each group has a different pulse width than IRQ signals associated with other groups.

4. The device of claim 1, wherein the single line IRQ bus is an asynchronous bus.

5. The device of claim 1, wherein the single line IRQ bus is dedicated to unidirectional signal transmissions from the slave devices to the master device.

6. The device of claim 1, wherein the control data bus comprises an Inter-Integrated Circuit (I2C) serial bus, a camera control interface (CCI) serial bus, or CCI extension (CCIe) serial bus.

7. The device of claim 1, wherein the control data bus supports bidirectional signaling between the slave devices and the master device.

8. A method operational on a master device, comprising:

grouping slave devices coupled to a shared single line interrupt request (IRQ) bus into one or more groups, where each group is associated with a different IRQ signal;

monitoring the IRQ bus to ascertain when an IRQ signal is asserted by one or more of the slave devices;

identifying a group with which the IRQ signal is associated; and

scanning at least one slave device in the identified group to ascertain an asserting slave device that asserted the IRQ signal on the IRQ bus.

9. The method of claim 8, wherein scanning the at least one slave device comprises:

scanning an IRQ status register of the asserting slave device.

10. The method of claim 8, further comprising:

granting the asserting slave device access to transmit data over a control data bus.

11. The method of claim 10, wherein the control data bus supports a bidirectional signaling between the slave devices and the master device.

12. The method of claim 8, wherein the IRQ signal associated with each group has a different pulse width than other IRQ signals associated with other groups.

13. The method of claim 8, wherein the IRQ bus operates asynchronously.

14. The method of claim 8, wherein the IRQ bus is dedicated to unidirectional signal transmissions from the slave devices to the master device.

15. The method of claim 8, wherein each of the one or more groups includes at least one slave device.

16. A slave device, comprising:

a first interface to a single line interrupt request (IRQ) bus to which a master device is coupled;

a second interface to a control data bus to which the master device is also coupled; and

a processing circuit coupled to the first interface and the second interface, the processing circuit adapted to;

obtain a group assignment from a master device, wherein the group assignment identifies one group from a plurality of groups, each group being associated with a different IRQ signal;

monitor the IRQ bus to ascertain whether an IRQ signal is asserted by another slave device; and

assert a first IRQ signal on the IRQ bus when no other IRQ signal is asserted on the IRQ bus.

17. The slave device of claim 16, wherein the IRQ bus is dedicated to unidirectional signal transmissions from one or more slave devices to the master device.

18. The slave device of claim 16, wherein the control data supports bidirectional communications between one or more slave devices and the master device.

19. The slave device of claim 16, wherein the control data bus comprises an Inter-Integrated Circuit (I2C) serial bus, a camera control interface (CCI) serial bus, or CCI extension (CCIe) serial bus.

20. The slave device of claim 16, wherein each of the plurality of groups includes at least one slave device.

21. The slave device of claim 16, wherein the processing circuit is further adapted to:

deassert the first IRQ signal from the IRQ bus;

monitor the IRQ bus to determine whether a second IRQ signal is asserted on the IRQ bus by another slave device; and

reassert the first IRQ signal if the second IRQ signal is asserted on the IRQ bus, wherein the first IRQ signal is reasserted after the IRQ bus becomes idle.

22. The slave device of claim 16, wherein the processing circuit is further adapted to:

receive a status register query from the master device via the control data bus; and

respond with a status indication that the slave device asserted the first IRQ signal on the IRQ bus.

23. A method operational on a slave device, comprising:

obtaining a group assignment from a master device, wherein the group assignment identifies one group from a plurality of groups, each group being associated with a different interrupt request (IRQ) signal;

monitoring a single line IRQ bus to ascertain whether an IRQ signal is asserted by one of the other slave devices; and

asserting a first IRQ signal on the IRQ bus when no other IRQ signal is asserted on the IRQ bus.

24. The method of claim 23, wherein the IRQ bus is an asynchronous bus.

25. The method of claim 23, wherein the IRQ bus is dedicated to unidirectional signal transmissions from slave devices to the master device.

26. The method of claim 23, wherein each of the plurality of groups includes at least one slave device.

27. The method of claim 23, further comprising:

deasserting the first IRQ signal from the IRQ bus;

monitoring the IRQ bus to ascertain whether another device is asserting a second IRQ signal on the IRQ bus; and

reasserting the first IRQ signal if the other device is asserting the second IRQ signal, wherein the first IRQ signal is reasserted after the second IRQ signal is deasserted.

28. The method of claim 23, further comprising:

receiving a status register query from the master device via a control data bus; and

responding with a status indication that the slave device asserted the first IRQ signal on the IRQ bus.

29. The method of claim 28, wherein a control data bus is a CCIe-compatible bus.

30. The method of claim 28, wherein a control data bus is a bidirectional bus between the slave devices and the master device.