RELOCATING DATA BASED ON MATCHING ADDRESS SEQUENCES

• US 20150058535A1
• Filed: 05/22/2014
• Published: 02/26/2015
• Est. Priority Date: 08/21/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: LASSER, MENAHEM
• Granted Patent: US 9,003,108 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A controller of the data storage device is configured to store a first sequence of addresses based on a first sequence of read instructions received from a host device. Subsequent to storing the first sequence of addresses, the controller is configured to receive a second sequence of read instructions from the host device and to determine whether a second sequence of addresses that is based on the second sequence of read instructions matches the first sequence of addresses. The controller is configured to relocate at least one page of the non-volatile memory at least partially based on the second sequence of addresses matching the first sequence of addresses.

Claims

1. A method comprising:

in a memory device including a non-volatile memory including a three-dimensional (3D) memory and circuitry associated with operation of memory cells of the 3D memory, performing;

receiving a first sequence of read instructions from a host device;

storing a first sequence of addresses based on the first sequence of read instructions;

subsequent to storing the first sequence of addresses, receiving a second sequence of read instructions from the host device;

determining whether a second sequence of addresses that is based on the second sequence of read instructions matches the first sequence of addresses; and

relocating at least one page of the non-volatile memory at least partially based on the second sequence of addresses matching the first sequence of addresses,

wherein the first sequence of addresses is stored in a table of address sequences, and wherein the table is maintained by selecting a particular address sequence of the table for deletion based on a length of time since a most recent update of the particular address sequence, based on a counter value associated with the particular address sequence, or a combination thereof.

2. The method of claim 1, wherein the first sequence of read instructions is part of a sequence of read instructions that is received immediately after a boot event of the host device.

3. The method of claim 1, wherein the at least one page of the non-volatile memory is relocated from a block that is shared by another page corresponding to one of the addresses in the second sequence of addresses.

4. The method of claim 1, wherein storing the first sequence of addresses includes identifying a first particular address received from the host device as a starting address of the first sequence of addresses.

5. The method of claim 4, wherein the first particular address is identified as the starting address in response to the first particular address being a first address that is received following a boot event at the memory device.

6. The method of claim 4, wherein the first particular address is identified as the starting address in response to a first delay exceeding a first time threshold, the first delay corresponding to a length of time that no read instructions are received from the host device before receiving the first particular address.

7. The method of claim 1, further comprising identifying a second particular address received from the host device as an ending address of the first sequence of addresses.

8. The method of claim 7, wherein the second particular address is identified as the ending address in response to a second delay exceeding a second time threshold, the second delay corresponding to a length of time that no read instructions are received from the host device after receiving the second particular address.

9. The method of claim 7, wherein the second particular address is identified as the ending address in response to a number of addresses in the sequence of addresses from a beginning of the first sequence of addresses to the second particular address satisfying a sequence length threshold.

11. The method of claim 1, further comprising:

comparing an identified sequence of addresses to one or more address sequences of the table;

in response to determining that an address sequence of the table matches the identified sequence, incrementing a counter associated with the address sequence; and

in response to determining that no address sequence of the table matches the identified sequence, adding the identified sequence to the table.

13. The method of claim 1, wherein the first sequence of addresses includes logical addresses of data requested by the host device.

14. The method of claim 1, wherein relocating the at least one page is performed further based on reading data from a block of the non-volatile memory that includes the at least one page and determining that a measurement of errors in the data satisfies an error threshold.

15. The method of claim 1, wherein relocating the at least one page is performed further based on determining that a counter value associated with the stored sequence exceeds a read count threshold.

10. (canceled)

12. (canceled)

16-18. -18. (canceled)

19. A data storage device comprising:

a non-volatile memory that includes a three-dimensional (3D) memory; and

a controller coupled to the non-volatile memory,

wherein the controller is associated with operation of memory cells of the 3D memory and is configured to store a first sequence of addresses based on a first sequence of read instructions received from a host device and, subsequent to storing the first sequence of addresses, to receive a second sequence of read instructions from the host device and to determine whether a second sequence of addresses that is based on the second sequence of read instructions matches the first sequence of addresses,

wherein the controller is configured to relocate at least one page of the non-volatile memory at least partially based on the second sequence of addresses matching the first sequence of addresses,

wherein the first sequence of addresses is stored in a table of address sequences that is maintained by the controller,

wherein the controller is configured to compare an identified sequence of addresses to one or more address sequences of the table and to increment a counter associated with an address sequence of the table in response to determining that the address sequence matches the identified sequence, and

wherein the controller is configured to add the identified sequence to the table in response to determining that no address sequence of the table matches the identified sequence.

20. The data storage device of claim 19, wherein the first sequence of read instructions is part of a sequence of read instructions that is received immediately after a boot event of the host device.

21. The data storage device of claim 19, wherein the controller is configured to relocate at least one page of the non-volatile memory from a block that is shared by another page corresponding to one of the addresses in the second sequence of addresses.

22. The data storage device of claim 19, wherein the controller is configured to identify a first particular address received from the host device as a starting address of the first sequence of addresses.

23. The data storage device of claim 22, wherein the controller is configured to identify the first particular address as the starting address in response to the first particular address being a first address that is received following a boot event at the memory device.

24. The data storage device of claim 22, wherein the controller is configured to identify the first particular address as the starting address in response to a first delay exceeding a first time threshold, the first delay corresponding to a length of time that no read instructions are received from the host device before receiving the first particular address.

25. The data storage device of claim 19, wherein the controller is configured to identify a second particular address received from the host device as an ending address of the first sequence of addresses.

26. The data storage device of claim 25, wherein the controller is configured to identify the second particular address as the ending address in response to a second delay exceeding a second time threshold, the second delay corresponding to a length of time that no read instructions are received from the host device after receiving the second particular address.

27. The data storage device of claim 25, wherein the controller is configured to identify the second particular address as the ending address in response to a number of addresses in the sequence of addresses from a beginning of the first sequence of addresses to the second particular address satisfying a sequence length threshold.

30. The data storage device of claim 19, wherein the controller is configured to select a particular address sequence of the table for deletion based on a length of time since a most recent update of the particular address sequence, based on a counter value associated with the particular address sequence, or a combination thereof.

34. The data storage device of claim 19, wherein the controller is configured to relocate the at least one page further based on a time measure associated with the stored sequence exceeding a time threshold.

35. The data storage device of claim 34, wherein the time measure corresponds to an amount of calendar time since a most recent relocation of the at least one page.

36. The data storage device of claim 34, wherein the time measure corresponds to an accumulated power-on duration of the memory device since a most recent relocation of the at least one page.

28-29. -29. (canceled)

31-33. -33. (canceled)

37. A method comprising:

in a memory device including a non-volatile memory including a three-dimensional (3D) memory and circuitry associated with operation of memory cells of the 3D memory, performing;

receiving a first sequence of read instructions from a host device;

identifying a particular address of the first sequence as an ending address in response to a delay exceeding a time threshold, the delay corresponding to a length of time that no read instructions are received from the host device after receiving the particular address;

storing a first sequence of addresses based on the first sequence of read instructions;

subsequent to storing the first sequence of addresses, receiving a second sequence of read instructions from the host device;

determining whether a second sequence of addresses that is based on the second sequence of read instructions matches the first sequence of addresses; and

relocating at least one page of the non-volatile memory at least partially based on the second sequence of addresses matching the first sequence of addresses.

38. The method of claim 37, wherein the first sequence of read instructions is part of a sequence of read instructions that is received immediately after a boot event of the host device.

39. The method of claim 37, wherein storing the first sequence of addresses includes identifying a second particular address received from the host device as a starting address of the first sequence of addresses.

40. The method of claim 39, wherein the second particular address is identified as the starting address in response to a second delay exceeding a second time threshold, the second delay corresponding to a length of time that no read instructions are received from the host device before receiving the second particular address.