DETECTION OF MULTIPLE ACCESSES TO A ROW ADDRESS OF A DYNAMIC MEMORY WITHIN A REFRESH PERIOD

• US 20150058549A1
• Filed: 08/20/2013
• Published: 02/26/2015
• Est. Priority Date: 08/20/2013
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Jeffrey, David, Fang, Clement, Park, Heechoul, Grohoski, Gregory F., Duncan, Neil, Cheng, Lik
• Granted Patent: US 9,355,689 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Claims

1. An apparatus, comprising:

a memory including a plurality of entries, wherein each entry of the plurality of entries is configured to store a row address;

a first plurality of counters, wherein each counter of the first plurality of counters is coupled to a respective entry of the plurality of entries in the memory;

a second plurality of counters, wherein each counter of the second plurality of counters is coupled to the respective entry of the plurality of entries in the memory; and

a control circuit configured to;

receive a row address used to access a dynamic memory;

store the row address in an entry of the plurality of entries responsive to a determination that the received row address has not been previously stored in the memory;

change, responsive to a determination that the received row address has been previously stored in an entry of the memory, a value of a counter of the first plurality of counters corresponding to the entry of the memory;

change a value of each counter of the second plurality of counters responsive to a determination that a pre-determined time interval has elapsed; and

initiate a refresh of the dynamic memory responsive dependent upon the value of the counter of the first plurality of counters corresponding to the entry of the memory and the value of the counter of the second plurality of counters corresponding to the entry of the memory.

2. The apparatus of claim 1, wherein to initiate the refresh of the dynamic memory, the control circuit is further configured to send a refresh signal to the dynamic memory.

3. The apparatus of claim 1, wherein to initiate the refresh of the dynamic memory, the control circuit is further configured to retire the entry of the plurality of entries corresponding to the received row address from the memory.

4. The apparatus of claim 3, wherein to retire the entry, the control circuit is further configured to reset a status bit, wherein the status bit indicates the entry is available for storing a new row address.

5. The apparatus of claim 2, wherein to store the received row address, the control circuit is further configured to determine for each entry of the plurality of entries storing a row address, an amount of time the row address has been stored.

6. The apparatus of claim 5, wherein the amount of time is dependent upon a value of respective one of the second plurality of counters.

7. The apparatus of claim 1, wherein to change the value of the counter of the first plurality of counters, the control circuit is further configured to increment the counter of the first plurality of counters.

8. A method for operation a cache circuit, comprising:

receiving a row address, wherein the row address corresponds to a target row within a dynamic random access memory (DRAM);

storing the received row address responsive to a determination that the received row address has not been previously received;

determining a number of times the row address has been received responsive to a determination that the received row address has been previously received;

determining how long the row address has been stored responsive to the determination that the row address has been previously received; and

initiating a refresh of one or more victim rows within the DRAM dependent upon the number of times the row address has been received, wherein each victim row of the one or more victim rows within the DRAM is adjacent to the target row.

9. The method of claim 8, wherein initiating the refresh of the one or more rows comprises signaling a processor coupled to the DRAM to refresh the DRAM.

10. The method of claim 8, wherein storing the received row address comprises moving one of one or more previously stored row addresses to one of a plurality of entries in an overflow counter.

11. The method of claim 10, wherein moving the one of the one or more previously stored row addresses comprises determining an amount time each one of the one or more previously stored row addresses has been stored.

12. The method of claim 11, wherein determining the number of times the row address has been received further comprises incrementing a respective one of a first plurality of counters.

13. The method of claim 12, further comprising incrementing a respective one of a second plurality counters responsive to a determination that, after a pre-determined time interval has elapsed, a value stored in a corresponding one of the first plurality of counters is larger than a pre-determined value.

14. The method of claim 11, wherein storing the received address comprises storing the received address in a Content-Addressable Memory (CAM).

15. A system, comprising:

a processor;

one or more dynamic random access memories (DRAMs), wherein each one of the one or more DRAMs is coupled to the processor; and

a row address cache circuit coupled to the processor, wherein the row address cache circuit is configured to;

receive a row address used to access at least one of the one or more DRAMs;

store the received row address responsive to a determination that the received row address has not been previously received;

determine a number of times the row address has been received responsive to a determination that the received row address has been previously received;

determine how long the row address has been stored responsive to the determination that the row address has been previously received; and

initiate a refresh of the at least one of the one or more DRAMs dependent upon the determined number of times the row address has been received and dependent upon how long the row address has been stored.

16. The system of claim 15, wherein to initiate the refresh the row address cache circuit is further configured to send a signal to the processor, wherein the signal includes a request for the processor to refresh at least one of the one or more DRAMs.

17. The system of claim 15, wherein the row address cache circuit comprises a memory, wherein the memory includes a plurality of entries.

18. The system of claim 17, wherein to store the row address, the row address cache circuit is further configured to store the received row address in an entry of the plurality of entries.

19. The system of claim 17, wherein the row address cache circuit is further configured to retire an entry of the plurality of entries of the memory corresponding to the received row address responsive to the initiation of the refresh of the at least one or more DRAMs.

20. The system of claim 15, wherein the row address cache circuit is further configured to increment a plurality of counters after a pre-determined time, wherein each counter of the plurality of counters corresponds to an entry of the plurality of entries storing a row address.