SEMICONDUCTOR MEMORY APPARATUS

• US 20150058566A1
• Filed: 11/15/2013
• Published: 02/26/2015
• Est. Priority Date: 08/22/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: YOON, Jung Hyuk, SHIN, Yoon Jae
• Granted Patent: US 9,659,640 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods

Abstract

A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Claims

1. A semiconductor memory apparatus comprising:

a column address decoding unit configured to decode a column address and generate a column select signal;

a row address decoding unit configured to decode a row address and generate a word line select signal;

a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal;

a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and

a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

2. The semiconductor memory apparatus according to claim 1,

wherein the driving driver unit comprises:

a driving driver configured to provide a driving voltage in response to the column select signal; and

a plurality of first resistor elements electrically coupled in series to voltage-divide an output of the driving driver, and

wherein a lower voltage is provided to a resistive memory element distant from the driving driver rather than to a resistive memory element close to the driving driver.

3. The semiconductor memory apparatus according to claim 2, wherein, in the driving driver unit, the plurality of resistive memory elements are respectively electrically coupled to nodes where the plurality of first resistor elements electrically coupled in series are electrically coupled with each other.

4. The semiconductor memory apparatus according to claim 3, wherein a read write circuit unit is electrically coupled to a node where a last resistor element, most distant from the driving unit, among the plurality of first resistor elements electrically coupled in series and a resistor memory element are electrically coupled.

5. The semiconductor memory apparatus according to claim 2, wherein the sink current control unit provides a sink voltage with a higher voltage level to a current sink unit which is electrically coupled with a resistive memory element, as a distance between the driving driver and the resistive memory element increases.

6. The semiconductor memory apparatus according to claim 5,

wherein the sink current control unit generates the plurality of sink voltages with voltage levels between a first word line driving voltage and a second word line driving voltage, and

wherein the sink current control unit outputs a sink voltage selected among the plurality of sink voltages in response to the word line select signal.

7. The semiconductor memory apparatus according to claim 6,

wherein the sink current control unit is applied with the first and second word line driving voltages on both ends of a plurality of second resistor elements which are electrically coupled in series, and

wherein the sink current control unit includes a plurality of switching sections which output voltages of nodes where the plurality of second resistor elements are electrically coupled, in response to the word line select signal.

8. A semiconductor memory apparatus comprising:

a driving driver unit configured to provide voltages with different voltage levels to a plurality of resistive memory elements, respectively, in response to a column select signal;

a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to a plurality of sink voltages; and

a sink current control unit configured to generate the plurality of sink voltages with different voltage levels in response to a plurality of word line select signals.

9. The semiconductor memory apparatus according to claim 8,

wherein the driving driver unit comprises:

a driving driver configured to provide a driving voltage in response to the column select signal, and

wherein the voltages with different voltage levels are provided to the plurality of respective resistive memory elements according to distances between the driving driver and the plurality of respective resistive memory elements.

10. The semiconductor memory apparatus according to claim 9, wherein the driving driver unit provides a voltage with a lower voltage level to a resistive memory element distant from the driving driver rather than to a resistive memory element close to the driving driver.

11. The semiconductor memory apparatus according to claim 9, wherein the plurality of current sink units are configured such that a current sink unit electrically coupled with the resistive memory element distant from the driving driver is applied with a sink voltage with a higher voltage level than a current sink unit electrically coupled with the resistive memory element close to the driving driver.

12. The semiconductor memory apparatus according to claim 9, wherein the sink current control unit outputs one of the plurality of sink voltages in response to a word line select signal which is enabled among the plurality of word line select signals.

13. The semiconductor memory apparatus according to claim 12, wherein the sink current control unit is configured to provide a sink voltage with a higher voltage level to the current sink unit electrically coupled with the resistive memory element distant from the driving driver than the current sink unit electrically coupled with the resistive memory element close to the driving driver.

14. The semiconductor memory apparatus according to claim 13, wherein the sink current control unit comprises:

a voltage supply signal generating section configured to generate a voltage supply signal when even one of the plurality of word line select signals is enabled;

a voltage dividing section configured to supply a first word line driving voltage and a second word line driving voltage to both ends, respectively, of a plurality of resistor elements electrically coupled in series, in response to the voltage supply signal, and generate the plurality of sink voltages; and

a plurality of switching sections configured to output one of the plurality of sink voltages in response to a word line select signal which is enabled among the plurality of word line select signals.

15. A semiconductor memory apparatus comprising:

a driving driver unit configured to provide voltages with different voltage levels to a plurality of respective resistive memory elements in response to a column select signal;

a plurality of current sink units configured to flow current from one of the plurality of resistive memory elements to a ground terminal in response to a plurality of word line select signals; and

a current sink control unit configured to flow different amounts of current from the plurality of current sink units to the ground terminal.

16. The semiconductor memory apparatus according to claim 15,

wherein the driving driver unit comprises:

a driving driver configured to provide a driving voltage in response to the column select signal; and

a plurality of resistor elements electrically coupled in series to be inputted with an output of the driving driver, and

wherein the resistive memory elements are electrically coupled to respective nodes where the plurality of resistor elements are electrically coupled.

17. The semiconductor memory apparatus according to claim 16,

wherein the plurality of current sink units are electrically coupled to the plurality of respective resistive memory elements, and

wherein one of the plurality of current sink units is activated in response to the plurality of word line select signals.

18. The semiconductor memory apparatus according to claim 17, wherein the current sink control unit differentiates amounts of current flowed by the plurality of current sink units electrically coupled to the plurality of respective resistive memory elements, according to respective distances between the driving driver and the plurality of resistive memory elements.

19. The semiconductor memory apparatus according to claim 18, wherein the current sink control unit is configured such that an amount of current flowed from a current sink unit electrically coupled with a resistive memory element close to the driving driver, to the ground terminal, is smaller than an amount of current flowed from a current sink unit electrically coupled with a resistive memory element distant from the driving driver.

20. The semiconductor memory apparatus according to claim 19,

wherein the current sink control unit comprises a plurality of resistor elements which are electrically coupled in series, and

wherein the plurality of resistor elements are respectively electrically coupled to the plurality of current sink units, and the ground terminal is electrically coupled to a resistor element which is farthest from the driving driver.

21. A microprocessor, comprising:

a control unit configured to receive a signal including a command from the outside and perform extraction or decryption of the command or input or output control;

an operation unit configured to perform an operation according to a decryption result of the command in the control unit; and

a storage unit configured to store one or more among data to be operated, data corresponding to a result of the operation, and an address for the data to be operated,

wherein the storage unit includes a semiconductor memory apparatus comprises;

a column address decoding unit configured to decode a column address and generate a column select signal;

a row address decoding unit configured to decode a row address and generate a word line select signal;

a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal;

a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and

a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

22. A processor, comprising:

a core unit configured to perform an operation corresponding to a command input from the outside using data according to the command;

a cache semiconductor device unit configured to store one or more among data to be operated, data corresponding to a result of the operation, and an address for the data to be operated; and

a bus interface configured to be connected between the core unit and the cache semiconductor device unit, and transmit data between the core unit and the cache semiconductor device unit,

wherein the cache semiconductor device unit includes a semiconductor memory apparatus comprising;

a driving driver unit configured to provide voltages with different voltage levels to a plurality of resistive memory elements, respectively, in response to a column select signal;

a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to a plurality of sink voltages; and

a sink current control unit configured to generate the plurality of sink voltages with different voltage levels in response to a plurality of word line select signals.

23. A processor, comprising:

a processor configured to interpret a command input from the outside and control an operation of information according to an interpretation result of the command;

an auxiliary storage device configured to store a program for interpretation of the command, and the information;

a main storage device configured to transfer the program and information from the auxiliary storage device and store the program and the information so that the processor performs the operation using the program and information when the program is executed; and

an interface device configured to perform communication between the outside and one or more among the processor, the auxiliary storage device, and the main storage device,

wherein at least one of the auxiliary storage device and the main storage device includes a semiconductor memory apparatus comprising;

a driving driver unit configured to provide voltages with different voltage levels to a plurality of respective resistive memory elements in response to a column select signal;

a plurality of current sink units configured to flow current from one of the plurality of resistive memory elements to a ground terminal in response to a plurality of word line select signals; and

a current sink control unit configured to flow different amounts of current from the plurality of current sink units to the ground terminal.