STORAGE DEVICE, CONTROLLER AND MEMORY CONTROLLING METHOD

• US 20150058697A1
• Filed: 08/22/2013
• Published: 02/26/2015
• Est. Priority Date: 08/22/2013
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: IWASAKI, Kiyotaka
• Application Number:
  US13/973,942
• Publication Number:
  US 20150058697A1
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

A nonvolatile memory device includes a plurality of memory regions, and a memory controller that controls data transfer operations to and from the memory regions. When generating an error checking and correcting code (ECC) for data including a plurality of data units and writing the data and the ECC in at least one of a plurality of memory regions, the memory controller acquires ECC information and adjusts a size of the data units and a size of the ECC on the basis of the acquired ECC information, to form a plurality of data frames each including the data unit and the ECC for the data unit.

Claims

1. A storage device comprising:

a plurality of memory regions; and

a memory controller configured to control data transfer operations to and from the memory regions,

wherein, when generating an error checking and correcting code (ECC) for data including a plurality of data units and writing the data and the ECC in at least one of the memory regions, the memory controller acquires ECC information and adjusts a size of the data units and a size of the ECC on the basis of the acquired ECC information, to form a plurality of data frames each including the data unit and the ECC for the data unit.

2. The device according to claim 1, wherein each memory region represents a page, and the memory controller adjusts the number of the data frames formed per page on the basis of the acquired ECC information.

3. The device according to claim 2, wherein

the acquired ECC information is information set according to a specification and characteristics of the memory regions, and includes at least one of a correction performance of the error checking and correcting code, a size of the data unit, a size of the data frame, and the number of the data frames formed per page.

4. The device according to claim 1, wherein

the memory controller divides one of the data frames into first and second portions, the first portion to be written into a first memory region and the second portion to be written into a second memory region.

5. The device according to claim 1, wherein

the memory controller transfers first data frames to a first memory region for writing therein and second data frames to a second memory region for writing therein, a first portion of a divisible data frame to the first memory region for writing therein, and a second portion of the divisible data frame to a second memory region for writing therein.

6. The device according to claim 5, wherein

the memory controller divides the divisible data frame into the first and second portions during transferring of the first data frames to the first memory region.

7. The device according to claim 6, wherein

the memory controller transfers the second portion to the second memory region before the second data frames are transferred to the second memory region.

8. The device according to claim 1, wherein

when a data frame is divided and portions thereof are transferred respectively to the two memory regions, a flag indicating that the data frame has been divided is added to the ECC information.

9. The device according to claim 1, further comprising a data storage region in which the ECC information is stored.

10. The device according to claim 1, wherein

the memory regions are memory regions of a NAND type flash memory.

11. A controller for generating an error checking and correcting code (ECC) frame for data to be written into pages of nonvolatile memory, comprising:

an ECC circuit; and

a nonvolatile memory region for storing parameters based on which the ECC circuit generates ECC.

12. The controller according to claim 11, wherein the parameters include a size of data unit that undergoes processing by the ECC circuit, a size of the data frame that includes the data unit and the ECC, and the number of data frames to be written per page of nonvolatile memory.

13. The controller according to claim 12, wherein the ECC circuit adjusts a size of a data frame based on the stored parameters.

14. The controller according to claim 12, wherein the ECC circuit adjusts a size of a data frame based on the stored parameters.

15. The controller according to claim 11, wherein the parameters include a flag that indicates whether a data frame generated by the ECC circuit is divisible.

16. A memory controlling method comprising:

transmitting a request to write data including a plurality of data units in at least one memory region, to a controller;

acquiring an error checking and correcting code (ECC) information;

generating an ECC for each of the data units based on the ECC information;

forming a plurality of ECC frames, each including a data unit and the ECC generated for the data unit based on the ECC information.

17. The method according to claim 16, wherein

the ECC information is information set according to a specification and characteristics of the memory, and includes at least one of a correction performance of the ECC, a size of the data unit, a size of the ECC frame, and the number of the ECC frames written per memory region.

18. The method according to claim 16, further comprising:

dividing one of the ECC frames into a first portion and a second portion; and

writing the first portion into a first memory region and the second portion into a second memory region.

19. The method according to claim 18, wherein

the ECC frames include first ECC frames written into the first memory region and second ECC frames written into the second memory region, and

the one of the ECC frames is divided when the first ECC frames are transferred to the first memory region for writing therein, and the second portion is transferred to the second memory region for writing therein before the second ECC frames are transferred to the second memory region for writing therein.

20. The method according to claim 18, further comprising:

setting a flag in the ECC information to indicate that the one of the ECC data frames is divided.