Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same

• US 20150058699A1
• Filed: 07/14/2014
• Published: 02/26/2015
• Est. Priority Date: 08/23/2013
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Yang, Tsung-Chieh
• Granted Patent: US 9,459,962 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 2211/109 Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A multiplexer is controlled to couple a DRAM (Dynamic Random Access Memory) to a buffer. A DMA (Direct Memory Access) controller is directed to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to a RAID-encoding (Redundant Array of Independent Disk-encoding) unit in multiple batches. After a first condition is satisfied, the processing unit controls the multiplexer to couple the RAID-encoding unit to the buffer and directs the RAID-encoding unit to output a vertical ECC (Error Correction Code) to the buffer through the multiplexer in at least one batch.

Claims

1. A method for accessing a storage unit of a flash memory, performed by a processing unit, comprising:

controlling a multiplexer to couple a DRAM (Dynamic Random Access Memory) to a buffer;

directing a DMA (Direct Memory Access) controller to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to a RAID-encoding (Redundant Array of Independent Disk-encoding) unit in a plurality of batches; and

after a first condition is satisfied, controlling the multiplexer to couple the RAID-encoding unit to the buffer and directing the RAID-encoding unit to output a vertical ECC (Error Correction Code) to the buffer through the multiplexer in at least one batch,

thereby enabling a storage-unit access interface to obtain the message and the vertical ECC from the buffer, generate a horizontal ECC according to every one of the message and the vertical ECC, and store the message, the vertical ECC, and the horizontal ECC associated with one of the message and the vertical ECC to a storage unit.

2. The method of claim 1, wherein the storage unit comprises a plurality of SLCs (Single-Level Cells) or TLCs (Triple-Level Cells), each SLC stores one bit of information, and each TLC stores three bits of information.

3. The method of claim 1, wherein the first condition is satisfied when a first counter value reaches a threshold, indicating a total number of message outputs.

4. The method of claim 1, wherein the message, the vertical ECC, and the horizontal ECC associated with one of the message and the vertical ECC form a RAID group.

5. The method of claim 4, further comprising:

after a second condition is satisfied, controlling the multiplexer to couple the DRAM to the buffer to continue data programming of the next RAID group.

6. The method of claim 5, wherein the second condition is satisfied when a second counter value reaches a threshold, indicating a total number of vertical ECC outputs.

7. A method for accessing a storage unit of a flash memory, performed by a storage-unit access interface, comprising:

obtaining a message and vertical ECC (Error Correction Code) from a buffer in a plurality of batches, where, in each batch, a specified length of the message or the vertical ECC is obtained;

generating horizontal ECC according to the obtained message or the vertical ECC for each batch; and

storing the message, the horizontal ECC associated with the message, the vertical ECC, and the horizontal ECC associated with the vertical ECC to a storage unit.

8. The method of claim 7, wherein the message, the horizontal ECC associated with the message, the vertical ECC, and the horizontal ECC associated with the vertical ECC form a RAID group.

9. The method of claim 8, wherein the vertical ECC is generated according to the message of the RAID (Redundant Array of Independent Disk) group by a RAID-encoding unit.

10. The method of claim 7, wherein the storage unit comprises a plurality of SLCs (Single-Level Cells) or TLCs (Triple-Level Cells), each SLC stores one bit of information, and each TLC stores three bits of information.

11. An apparatus for accessing a storage unit of a flash memory, comprising:

a multiplexer;

a buffer;

a RAID-encoding (Redundant Array of Independent Disk-encoding) unit, generating vertical ECC (Error Correction Code) according to original data; and

a processing unit, coupled to the multiplexer and the RAID-encoding unit, controlling the multiplexer to couple a DRAM (Dynamic Random Access Memory) to the buffer;

directing a DMA (Direct Memory Access) controller to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to the RAID-encoding (Redundant Array of Independent Disk-encoding) unit in a plurality of batches; and

, after a first condition is satisfied, controlling the multiplexer to couple the RAID-encoding unit to the buffer and directing the RAID-encoding unit to output the vertical ECC to the buffer through the multiplexer in at least one batch.

12. The apparatus of claim 11, further comprising:

a storage-unit access interface, coupled to a storage unit, obtaining the message and the vertical ECC from the buffer, generating a horizontal ECC according to every of the message and the vertical ECC, and storing the message, the horizontal ECC associated with the message, the vertical ECC, and the horizontal ECC associated with the vertical ECC to the storage unit.

13. The apparatus of claim 12, further comprising:

an arbiter,

wherein, the processing unit is coupled to the arbiter, and directs the arbiter to read the message and the vertical ECC from the buffer and program the message and the vertical ECC to the storage unit via a storage-unit access interface.

14. The apparatus of claim 13, wherein the arbiter activates a CE (Chip Enable) control signal of the storage-unit access interface, which is relevant to the storage unit, and transmits the read data and a data write address to the storage unit via a data line of the storage-unit access interface.

15. The apparatus of claim 12, wherein the storage unit comprises a plurality of SLCs (Single-Level Cells) or TLCs (Triple-Level Cells).

16. The apparatus of claim 11, wherein the first condition is satisfied when a first counter value reaches a threshold, indicating a total number of message outputs.

17. The apparatus of claim 11, wherein the message, the horizontal ECC associated with the message, the vertical ECC, and the horizontal ECC associated with the vertical ECC form a RAID group.

18. The apparatus of claim 11, wherein, after a second condition is satisfied, the processing unit controls the multiplexer to couple the DRAM to the buffer to continue data programming of the next RAID group.

19. The apparatus of claim 18, wherein the second condition is satisfied when a second counter value reaches a threshold, indicating a total number of vertical ECC outputs.