DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE

• US 20150060843A1
• Filed: 02/18/2014
• Published: 03/05/2015
• Est. Priority Date: 09/02/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: LEE, Jong-Chan, Khang, Yoon-Ho, Kang, Su-Hyoung, Kim, Dong-Jo, Cha, Myoung-Geun, Lee, Ji-Seon, Ji, Deuk-Myung
• Granted Patent: US 9,252,284 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.

Claims

1. A method of manufacturing a display substrate, the method comprising:

forming a gate electrode on a substrate;

forming an active pattern comprising an oxide semiconductor;

forming a first insulation layer pattern and a second insulation layer pattern sequentially on the active pattern, the first insulation layer pattern and the second insulation layer pattern overlapping the gate electrode; and

forming a third insulation layer covering the active pattern, the first insulation layer pattern, and the second insulation layer pattern,

wherein either the first insulation layer pattern or the second insulation layer pattern comprises aluminum oxide, and

wherein forming the first insulation layer pattern and the second insulation layer pattern comprises performing a backside exposure process using the gate electrode as an exposure mask.

2. The method of claim 1, wherein the first insulation layer pattern comprises aluminum oxide and the second insulation layer pattern comprises silicon oxide.

3. The method of claim 1, wherein forming the first insulation layer pattern and the second insulation layer pattern comprises:

sequentially forming a first insulation layer and a second insulation layer to cover the active pattern;

forming a photoresist layer on the second insulation layer;

forming a photoresist pattern by exposing the photoresist layer from a backside of the substrate by using the gate electrode as an exposure mask; and

partially removing the first insulation layer and the second insulation layer by using the photoresist pattern as an etching mask.

4. The method of claim 1, wherein each of the first insulation layer pattern and the second insulation layer pattern has a width substantially the same as a width of the gate electrode.

5. The method of claim 1, wherein forming the third insulation layer comprises implanting impurities into portions of the active pattern where the first insulation layer pattern and the second insulation layer pattern are not disposed.

6. The method of claim 5, wherein forming the third insulation layer comprises performing a plasma enhanced chemical vapor deposition process or a plasma enhanced atomic layer deposition process using a silicon source gas comprising hydrogen.

7. The method of claim 5, wherein implanting impurities comprises forming a first region, a second region, and a third region of the active pattern, and the first region has an impurity concentration and an electrical conductivity substantially smaller than those of the second region and the third region.

8. The method of claim 7, wherein the first insulation layer pattern and the second insulation layer pattern prevent or reduce a diffusion or a doping of the impurities into the first region of the active pattern.

9. The method of claim 1, further comprising implanting impurities into portions of the active pattern where the first insulation layer pattern and the second insulation layer pattern are not disposed, before forming the third insulation layer.

10. The method of claim 1, further comprising forming a fourth insulation layer pattern on the second insulation layer pattern.

11. The method of claim 1, wherein the active pattern comprises at least one of amorphous zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO).

12. The method of claim 1, further comprising forming a gate insulation layer covering the gate electrode, wherein the active pattern is disposed on the gate insulation layer.

13. A display substrate, comprising:

a substrate;

a gate electrode disposed on the substrate;

an active pattern comprising an oxide semiconductor, the active pattern comprising a first region, a second region, and a third region, the first region of the active pattern overlapping the gate electrode;

a first insulation layer pattern and a second insulation layer pattern disposed on the first region of the active pattern, the first insulation layer pattern and the second insulation layer pattern overlapping the gate electrode; and

a third insulation layer covering the active pattern, the first insulation layer pattern and the second insulation layer pattern,

wherein either the first insulation layer pattern or the second insulation layer pattern comprises aluminum oxide, and

wherein each of the first insulation layer pattern and the second insulation layer pattern has a width substantially the same as a width of the gate electrode.

14. The display substrate of claim 13, wherein the first region of the active pattern has a width substantially the same as the width of the first insulation layer pattern.

15. The display substrate of claim 13, wherein the first region has an impurity concentration and an electrical conductivity smaller than those of the second region and the third region.

16. The display substrate of claim 13, wherein the second region and the third region of the active pattern are self-aligned to not overlap the gate electrode.

17. The display substrate of claim 13, wherein the first insulation layer pattern and the second insulation layer pattern reduce a diffusion or a doping of the impurities from the third insulation layer into the first region of the active pattern.

18. The display substrate of claim 13, wherein the third insulation layer comprises at least one of silicon nitride and silicon oxy-nitride.

19. The display substrate of claim 13, further comprising a fourth insulation layer pattern disposed on the second insulation layer pattern.

20. The display substrate of claim 13, further comprising a gate insulation layer disposed between the gate electrode and the active pattern,

wherein the active pattern comprises at least one of amorphous zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO).