Metal Oxide Semiconductor (MOS) Capacitor with Improved Linearity

• US 20150061071A1
• Filed: 08/30/2013
• Published: 03/05/2015
• Est. Priority Date: 08/30/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Khalili, Alireza, Wang, Cheng-Han, Vahid Far, Mohammad B., Chen, Phoebe Peihong
• Granted Patent: US 9,716,188 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/0811 MIS diodes
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H02M 3/18 using capacitors or batteries which are alternately charged and discharged, e.g. charged in parallel and discharged in series

Abstract

A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

Claims

1. An apparatus comprising:

a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel; and

an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch.

2. The apparatus of claim 1, wherein the first and second capacitor pairs comprise first and second metal oxide semiconductor (MOS) capacitor pairs, respectively, and the at least one capacitor pair comprises at least one MOS capacitor pair.

3. The apparatus of claim 2, the main branch and the auxiliary branch biased by bias voltages to force the MOS capacitor pairs to operate in either depletion or oxide regions.

4. The apparatus of claim 3, the first and second MOS capacitor pairs having selected capacitance ratios.

5. The apparatus of claim 4, the at least one MOS capacitor pair having selected capacitance ratios.

6. The apparatus of claim 4, the first and second MOS capacitor pairs having selected capacitance ratios with respect to the at least one MOS capacitor pair.

7. The apparatus of claim 2, the first and second MOS capacitor pairs having selected capacitance ratios with respect to the at least one capacitor pair.

8. The apparatus of claim 2, the at least one signal path comprising a third signal path having a third MOS capacitor pair connected in series with reversed polarities and a fourth signal path having a fourth MOS capacitor pair connected in series with reversed polarities, the third and fourth signal paths connected in parallel with the main branch.

9. The apparatus of claim 8, the auxiliary branch biased by bias voltages to force the third and fourth MOS capacitor pairs to operate in either depletion or oxide regions.

10. An apparatus comprising:

means for providing capacitive linearity associated with a plurality of capacitors operating over a first voltage range; and

means for extending the capacitive linearity associated with the plurality of capacitors to a second voltage range, the means for extending coupled to the means for providing.

11. The apparatus of claim 10, the plurality of capacitors comprise a plurality metal oxide semiconductor (MOS) capacitor pairs.

12. The apparatus of claim 11, the means for providing and the means for extending comprising means for biasing to force the MOS capacitor pairs to operate in either depletion or oxide regions.

13. The apparatus of claim 12, the plurality of MOS capacitors having selected capacitance ratios.

14. The apparatus of claim 11, the means for providing comprising:

means for generating a first capacitance value from a first MOS capacitor pair connected in series with reversed polarities; and

means for generating a second capacitance value from a second MOS capacitor pair connected in series with reversed polarities, the means for generating the first and second capacitance values connected in parallel.

15. The apparatus of claim 14, the first and second MOS capacitor pairs having selected capacitance ratios.

16. The apparatus of claim 14, the means for extending comprising:

means for generating a third capacitance value from a third MOS capacitor pair connected in series with reversed polarities; and

means for generating a fourth capacitance from a fourth MOS capacitor pair connected in series with reversed polarities, the means for generating the third and fourth capacitances connected in parallel with the means for providing.