INTEGRATED CIRCUIT PROVIDING FAULT PREDICTION

• US 20150061707A1
• Filed: 08/28/2013
• Published: 03/05/2015
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: Sankaralingam, Karthikeyan, Balasubramanian, Raghuraman
• Granted Patent: US 9,500,705 B2
• Time in Patent Office: Days
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937

Abstract

The prediction of hardware failure is obtained by operating two redundant circuit modules while one circuit module is artificially aged. The output of the two circuit modules is compared and a discrepancy between outputs indicates a projected failure of the aged modules. Aging may be accomplished by one or a combination of lowering operating voltages and re-phasing a sampling clock to reduce slack time both of which provide increased sensitivity to gate delay.

Claims

3-1. The integrated circuit of claim 1 wherein steps (a)-(c) are repeated.

19. A method of predicting failure in an integrated circuit comprised of multiple gates subject to increased gate delay with age in the integrated circuit, the method comprising the steps of:

(a) momentarily and selectively stressing a first redundant circuit module of the integrated circuit in a manner mimicking age-increased gate delay without stressing a second redundant circuit module of the integrated circuit;

(b) capturing outputs from first and second redundant circuit modules during the stressing; and

(c) comparing the captured outputs to detect errors caused by the selective stressing.