SYSTEMS, SYSTEM COMPONENTS AND METHODS FOR OPERATING THE SAME

• US 20150062111A1
• Filed: 08/04/2014
• Published: 03/05/2015
• Est. Priority Date: 09/03/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jong-Ho Roh
• Inventors: ROH, Jong-Ho, KONG, Jae-Sop
• Granted Patent: US 9,355,615 B2
• Time in Patent Office: Days
• US Class Current: 345/213
• CPC Class Codes: G06F 3/147 using display panels
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 2370/04 Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

In one embodiment, the converter is configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal. The second sync signal is for controlling image sensing.

Claims

1. A converter configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal, the second sync signal for controlling image sensing.

2. The converter of claim 1, wherein the first sync signal indicates a display frame rate.

3. The converter of claim 2, wherein the second sync signal is for controlling an image sensing frame rate.

4. The converter of claim 3, wherein the converter is configured to down convert the first sync signal to produce the second sync signal.

5. The converter of claim 3, wherein the converter is configured to up convert the first sync signal to produce the second sync signal.

6. The converter of claim 3, wherein the converter is configured to convert the first sync signal into the second sync signal based on conversion information.

7. The converter of claim 6, comprising:

a programmable memory configured to store the conversion information.

8. The converter of claim 7, wherein the conversion information indicates at least one of a conversion ratio between the first and second sync signals, a timing difference between the first and second sync signals, a format difference between the first and second sync signals and a protocol difference between the first and second sync signals.

9. The converter of claim 6, wherein the conversion information indicates at least one of a conversion ratio between the first and second sync signals, a timing difference between the first and second sync signals, a format difference between the first and second sync signals and a protocol difference between the first and second sync signals.

10. The converter of claim 3, wherein the converter is configured to generate the second sync signal such that the second sync signal has a different timing from the first sync signal.

11. The converter of claim 3, wherein the converter is configured to generate the second sync signal such that the second sync signal has a different frequency from the first sync signal.

12. The converter of claim 3, wherein the converter is configured to generate the second sync signal such that the second sync signal has a different format from the first sync signal.

13. The converter of claim 3, wherein the converter is configured to generate the second sync signal such that the second sync signal conforms to a different protocol than the first sync signal.

14. An application processor, comprising:

a first interface configured to interface with an image sensor;

a second interface configured to interface with a display driver; and

a converter configured to convert a first sync signal into a second sync signal, the first sync signal received from the display driver, and the second sync signal for controlling the image sensor.

15. The application processor of claim 14, wherein the first sync signal indicates a display frame rate of a display controlled by the display driver, and the second sync signal is for controlling an image sensing frame rate of the image sensor.

16. The application processor of claim 14, further comprising:

an image processing circuit configured to process image data received by the first interface and supply the processed image data to the second interface.

17. The application processor of claim 14, wherein the application processor is configured to transfer image data received by the first interface to the second interface without storing the image data in memory separate from the application processor.

18. The application processor of claim 14, further comprising:

a multimedia system configured to perform at least one multimedia function, and the multimedia system including the converter.

19. The application processor of claim 18, further comprising:

a central processing unit operationally connected to the multimedia system.

20. The application processor of claim 19, wherein the central processing unit includes a plurality of cores, and the application processor further includes, a power management unit configured to control which of the plurality of cores is enabled.

21-36. -36. (canceled)