APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS

• US 20150063022A1
• Filed: 11/14/2014
• Published: 03/05/2015
• Est. Priority Date: 08/21/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Granted Patent: US 9,779,791 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

Claims

1. A memory device comprising:

an array of memory cells having a plurality of memory blocks, each memory block having a plurality of sub-blocks of memory cells; and

control circuitry coupled to the array of memory cells, the control circuitry configured to access a first sub-block of memory cells and a second sub-block of memory cells at the same time, wherein the first and second sub-blocks of memory cells are part of a block of memory cells of a plurality of blocks of memory cells of a memory array wherein the first sub-block of the block of memory cells and the second sub-block of the block of memory cells are not in the same row or the same column of the block of memory cells.

2. The memory device of claim 1, wherein the array of memory cells is an array of dynamic random access memory cells.

3. The memory device of claim 1, wherein the array of memory cells is an array of phase change memory cells.

4. The memory device of claim 1, wherein the array of memory cells are organized as a NAND array of memory cells.

5. The memory device of claim 1, further comprising a decoder circuit coupled to the array of memory cells and configured to enable a plurality of decoding signal lines to provide enable signals in response to decoding signals from the control circuitry.

6. The memory device of claim 1, further comprising driver circuits coupled to the control circuitry through a control logic circuit, wherein the driver circuits are configured to output signals from the array of memory cells in response to control signals from the control circuitry.

7. The memory device of claim 6, further comprising a sense/cache circuit coupled between the array of memory cells and the driver circuits.

8. A memory device comprising:

an array of memory cells having a plurality of two-dimensional arrays of memory cells, each two-dimensional array of memory cells having a plurality of sub-blocks; and

control circuitry coupled to the array of memory cells, the control circuitry configured to access the plurality of sub-blocks of memory cells in a respective two-dimensional array at the same time, the accessed sub-blocks being separated from each other by sub-blocks in the array that are not being accessed such that no accessed sub-block of the plurality of sub-blocks is in a same row or column as another simultaneously accessed sub-block of the plurality of sub-blocks and wherein the accessed sub-blocks in the array or memory cells occupy the same respective location in each of the two-dimensional arrays.

9. The memory device of claim 8, wherein the control circuitry is further configured to enable access lines coupled to the memory cells in the sub-blocks to receive programming voltages, read voltages, or erase voltages.

10. The memory device of claim 8, further comprising decoder circuits and the control circuitry is further configured to provide an enable signal for each enabled sub-block in response to a plurality of decoding signals from the decoder circuit.

11. The memory device of claim 8, wherein the array of memory cells is a three dimensional array of memory cells.

12. The memory device of claim 8, wherein each of the memory cells in the array of memory cells is defined with reference to a first coordinate and a second coordinate in a coordinate system.

13. The memory device of claim 12, wherein each memory cell in the two-dimensional arrays is located with reference to an x-coordinate and a y-coordinate in a Cartesian coordinate system.

14. The memory device of claim 8, wherein the memory cells are located according to a Polar coordinate system.

15. A memory device comprising:

an array of memory cells having a plurality of memory blocks, each memory block having rows and columns of sub-blocks of memory cells; and

control circuitry coupled to the array of memory cells, the control circuitry configured to receive a memory request and, in response to the memory request, access first data in a first sub-block of memory cells of a block of memory cells, access second data in a second sub-block of memory cells of the block of cells at the same time that the first data is being accessed, wherein the second sub-block is in a row of sub-blocks and a column of sub-blocks of the memory array that do not include the first sub-block.

16. The memory device of claim 15, wherein the control circuit configured to access the first data comprises the control circuit configured to write the first data to memory cells of the first sub-block and the control circuit configured to access the second data comprises the control circuit configured to write the second data to memory cells of the second sub-block.

17. The memory device of claim 15, wherein the control circuit configured to access the first data comprises the control circuit configured to erase the first data from memory cells of the first sub-block and the control circuit configured to access the second data comprises the control circuit configured to erase the second data from memory cells of the second sub-block.

18. The memory device of claim 15, wherein the control circuit configured to access the first data comprises the control circuit configured to read the first data from memory cells of the first sub-block and the control circuit configured to access the second data comprises the control circuit configured to read the second data from memory cells of the second sub-block.

19. A memory system comprising:

an array of memory cells having a plurality of memory blocks, each memory block having a plurality of sub-blocks of memory cells; and

control circuitry coupled to the array of memory cells, the control circuitry configured to enable the plurality of sub-blocks of memory cells to be accessed at the same time, each of the enabled sub-blocks being adjacent only to sub-blocks of memory cells in the memory array that are not enabled to be accessed wherein no sub-block of the plurality of enabled sub-blocks in the memory block is in a same row or column as another simultaneously enabled sub-block of the plurality of enabled sub-blocks in the memory block.

20. The memory system of claim 19, wherein the control circuit is further configured to provide an enable signal for each enabled sub-block in response to a plurality of decoding signals in a decoder circuit.