Apparatus and Method for Power MOS Transistor

• US 20150064868A1
• Filed: 10/29/2014
• Published: 03/05/2015
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Su, Po-Chih, Liu, Ruey-Hsin
• Granted Patent: US 9,048,255 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/10 with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A method comprises forming a first trench and a second trench, depositing a dielectric material in a lower portion of the first trench, depositing a gate electrode material in the second trench and an upper portion of the first trench, forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench and forming an accumulation layer along a sidewall of the second trench.

Claims

1. A method comprising:

providing a semiconductor device comprising;

a first trench comprising;

a dielectric layer formed in a lower portion of the first trench; and

a first gate region formed in an upper portion of the first trench;

a first N+ region and a second N+ region on opposite sides of the first trench; and

a second trench adjacent to the second N+ region, wherein a gate electrode material is filled in the second trench; and

forming accumulation layer along a sidewall of the second trench.

2. The method of claim 1, wherein:

the second N+ region is a drain region; and

the first N+ region is a source region.

3. The method of claim 2, wherein:

the drain region is formed over an epitaxial layer; and

the epitaxial layer is formed over a buried layer.

4. The method of claim 3, wherein:

a bottom surface of the first trench is lower than a bottom surface of the epitaxial layer; and

a bottom surface of the second trench is lower than the bottom surface of the epitaxial layer.

5. The method of claim 4, wherein:

the bottom surface of the first trench is substantially level with the bottom surface of the second trench.

6. The method of claim 4, wherein:

the first trench and the second trench extend partially through the buried layer.

7. The method of claim 1, further comprising:

attracting majority carriers to generate the accumulation layer.

8. The method of claim 1, further comprising:

forming a low resistance drain current conductive path through the accumulation layer.

9. The method of claim 1, wherein:

the dielectric layer comprises an oxide.

10. The method of claim 1, wherein:

the semiconductor device is a quasi-vertical MOS transistor.

11. A method comprising:

forming a first trench and a second trench;

depositing a dielectric material in a lower portion of the first trench;

depositing a gate electrode material in the second trench and an upper portion of the first trench;

forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench; and

forming an accumulation layer along a sidewall of the second trench.

12. The method of claim 11, further comprising:

forming a buried layer over a substrate;

growing an epitaxial layer from the buried layer; and

forming the first trench and the second trench in the epitaxial layer and the buried layer.

13. The method of claim 12, wherein:

the first trench and the second trench extend through the epitaxial layer and extend partially through the buried layer.

14. The method of claim 11, further comprising:

attracting majority carriers to generate the accumulation layer.

15. The method of claim 11, wherein:

the gate material is polysilicon.

16. A method comprising:

forming a buried layer over a substrate;

growing an epitaxial layer over the buried layer;

forming a first trench and a second trench in the epitaxial layer and the buried layer, wherein;

a width of the second trench is greater than a width of the first trench;

forming a dielectric layer in a lower portion of the first trench;

depositing a gate electrode material in the second trench and an upper portion of the first trench; and

forming an accumulation layer along a sidewall of the second trench.

17. The method of claim 16, further comprising:

implanting ions into the epitaxial layer on a first side of the first trench to form a body region;

forming a first N+ region over the body region on the first side of the first trench; and

forming a second N+ region over the epitaxial layer on a second side of the first trench.

18. The method of claim 17, wherein:

the first N+ region and the second N+ region are on opposite sides of the first trench.

19. The method of claim 16, further comprising:

depositing a dielectric material into the first trench and the second trench until the first trench is fully filled with the dielectric material and the second trench is partially filled with the dielectric material.

20. The method of claim 16, further comprising:

generating the accumulation layer through attracting majority carriers.