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Apparatus and Method for Power MOS Transistor

  • US 20150064868A1
  • Filed: 10/29/2014
  • Published: 03/05/2015
  • Est. Priority Date: 07/11/2012
  • Status: Active Grant
First Claim
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1. A method comprising:

  • providing a semiconductor device comprising;

    a first trench comprising;

    a dielectric layer formed in a lower portion of the first trench; and

    a first gate region formed in an upper portion of the first trench;

    a first N+ region and a second N+ region on opposite sides of the first trench; and

    a second trench adjacent to the second N+ region, wherein a gate electrode material is filled in the second trench; and

    forming accumulation layer along a sidewall of the second trench.

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