Triple Patterning NAND Flash Memory

• US 20150064906A1
• Filed: 09/04/2013
• Published: 03/05/2015
• Est. Priority Date: 09/04/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sel, Jongsun, Pham, Tuan Duc, Hong, Mun Pyo
• Granted Patent: US 9,613,806 B2
• Time in Patent Office: Days
• US Class Current: 438/694
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Claims

1. A method of forming a hard mask layer comprising:

forming a plurality of mandrels that have a lateral dimension D which is defined by a photolithographic process and which are separated by spaces having a lateral dimension equal to D;

subsequently forming sidewall spacers along sides of the mandrels, gaps between neighboring sidewall spacers having a lateral dimension approximately equal to D/3;

subsequently depositing a first hard mask layer to fill the gaps between sidewall spacers;

subsequently etching the plurality of mandrels;

subsequently depositing a second hard mask layer to partially fill openings where the plurality of mandrels were etched;

subsequently etching back hard mask material of at least the second hard mask layer to leave first hard mask portions filling the gaps between sidewall spacers and second hard mask portions that extend along sidewall spacers on one side and are exposed on another side; and

subsequently removing the sidewall spacers.

2. The method of claim 1 wherein an individual mandrel is formed of a lower layer of amorphous Silicon and an upper layer of Silicon Nitride.

3. The method of claim 2 wherein etching the plurality of mandrels removes the upper layer of Silicon Nitride from the plurality of mandrels while leaving the lower layer of amorphous Silicon substantially intact.

4. The method of claim 3 wherein the plurality of mandrels, and the sidewall spacers, are formed on a Silicon Nitride etch stop layer.

5. The method of claim 4 further comprising, subsequent to removing the sidewall spacers, etching through the Silicon Nitride etch stop layer according to a pattern established by the first and second hard mask portions.

6. The method of claim 1 wherein the first hard mask layer and the second hard mask layer are formed of amorphous Silicon.

7. The method of claim 1 wherein the sidewall spacers are formed of Silicon Dioxide.

8. The method of claim 1 wherein the plurality of mandrels consist of Silicon Nitride, the sidewall spacers are formed of Silicon Dioxide, the first hard mask layer and the second hard mask layer are formed of amorphous Silicon, and wherein a layer of amorphous Silicon directly underlies the plurality of mandrels and the sidewall spacers.

9. The method of claim 8 wherein etching the plurality of mandrels removes the plurality of mandrels to expose the layer of amorphous Silicon.

10. The method of claim 9 wherein the second hard mask layer is deposited directly on exposed areas of the layer of amorphous Silicon.

11. The method of claim 1 wherein both the first and second hard mask portions have lateral dimensions of approximately D/3 and spacing of approximately D/3.

12. A method of forming an integrated circuit comprising:

forming a plurality of patterned portions using direct patterning photolithography;

subsequently forming sidewall spacers along sidewalls of the plurality of patterned portions;

subsequently filling gaps between sidewalls of neighboring patterned portions with first hard mask portions of a hard mask material;

subsequently removing the plurality of patterned portions;

subsequently forming second hard mask portions of the hard mask material in spaces where the plurality of patterned portions were removed, two second hard mask portions being formed in each space where an individual patterned portion was removed;

subsequently removing the sidewall spacers; and

subsequently using the first hard mask portions of the hard mask material and the second hard mask portions of the hard mask material to pattern one or more layers on a substrate.

13. The method of claim 12 wherein the patterned portions are formed of Silicon Nitride, or a combination of Silicon Nitride and amorphous Silicon.

14. The method of claim 13 wherein the sidewall spacers are formed of Silicon Dioxide.

15. The method of claim 14 wherein the first and second hard mask portions are formed of amorphous Silicon.

16. The method of claim 15 wherein a layer that directly underlies the sidewall spacers is formed of Silicon Dioxide.

17. The method of claim 12 wherein the plurality of patterned portions are formed having a lateral dimension D and wherein the first and second hard mask portions have a lateral dimension that is approximately one third of the lateral dimension D.

18. A method of forming an integrated circuit comprising:

forming a plurality of mandrels;

forming sidewall spacers along sides of the plurality of mandrels;

subsequently removing the plurality of mandrels;

subsequently depositing and etching a layer of sacrificial material to form first sacrificial portions between sidewall spacers and second sacrificial portions in openings where mandrels were removed, two second sacrificial portions formed per opening;

subsequently forming filler portions in gaps between second sacrificial portions;

subsequently removing the first and second sacrificial portions to leave the sidewall spacers and the filler portions; and

subsequently using the sidewall spacers and the filler portions as a hard mask to pattern one or more layers.

19. The method of claim 18 wherein the plurality of mandrels are formed of Silicon Dioxide.

20. The method of claim 18 wherein the sidewall spacers and the filler portions are formed of amorphous Silicon.

21. The method of claim 18 wherein the sacrificial material is Silicon Dioxide.

22. The method of claim 18 wherein the sidewall spacers and the filler portions are used as a hard mask to pattern an underlying layer of Silicon Nitride.