DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF

• US 20150067233A1
• Filed: 08/30/2013
• Published: 03/05/2015
• Est. Priority Date: 08/30/2013
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: CHENG, Chang-Kai
• Granted Patent: US 9,208,074 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A mapping table H2F update technique for a FLASH memory is disclosed. In the disclosed data storage device, when a master buffer block selected from a plurality of blocks of a FLASH memory to buffer write data from a host is full, the controller updates a logical-to-physical address mapping table for the master buffer block in separated update sub-intervals. Between the separated update sub-intervals, the controller responds to commands from the host. In this manner, commands from the host are responded to in a timely manner, without being postponed by a time-consuming mapping-table update of an entire buffer block.

Claims

1. A data storage device, comprising:

a FLASH memory, providing storage space divided into a plurality of blocks with each block comprising a plurality of pages; and

a controller, operating the FLASH memory in accordance with commands issued from a host,

wherein;

when a master buffer block selected from the plurality of blocks of the FLASH memory to buffer write data from the host is full, the controller updates a logical-to-physical address mapping table for the master buffer block in separated update sub-intervals; and

between the separated update sub-intervals, the controller responds to commands from the host.

2. The data storage device as claimed in claim 1, wherein:

the controller further selects a slave buffer block from the plurality of blocks of the FLASH memory; and

between the separated update sub-intervals, the controller uses the slave buffer block to buffer write data from the host.

3. The data storage device as claimed in claim 1, wherein:

in one update sub-interval, the controller updates the logical-to-physical address mapping relationship of M successive physical pages of the master buffer block, where M is a number.

4. The data storage device as claimed in claim 1, wherein:

in one update sub-interval, the controller updates the logical-to-physical address mapping relationship of P groups of logical addresses;

P is a number; and

the logical addresses belonging to the same group share the same physical page for storage of the logical-to-physical address mapping relationship.

5. The data storage device as claimed in claim 2, wherein:

after finishing the separated update sub-intervals for the master buffer block, the controller pushes the master buffer block into data blocks of the FLASH memory and uses the slave buffer block to play the role of the master buffer block and selects a spare block from the blocks of the FLASH memory to play the role of the slave buffer block.

6. A FLASH memory control method, comprising:

using a FLASH memory to provide storage space which is divided into a plurality of blocks, wherein each block comprises a plurality of pages;

operating the FLASH memory in accordance with commands issued from a host; and

when a master buffer block selected from the plurality of blocks of the FLASH memory to buffer write data from the host is full, updating a logical-to-physical address mapping table for the master buffer block in separated update sub-intervals,

wherein, between the separated update sub-intervals, commands from the host are responded to.

7. The FLASH memory control method as claimed in claim 6, further comprising:

selecting a slave buffer block from the plurality of blocks of the FLASH memory to buffer write data from the host between the separated update sub-intervals.

8. The FLASH memory control method as claimed in claim 6, wherein:

in one update sub-interval, updating the logical-to-physical address mapping relationship of M successive physical pages of the master buffer block; and

M is a number.

9. The FLASH memory control method as claimed in claim 6, wherein:

in one update sub-interval, updating the logical-to-physical address mapping relationship of P groups of logical addresses;

P is a number; and

the logical addresses belonging to the same group share the same physical page for storage of the logical-to-physical address mapping relationship.

10. The FLASH memory control method as claimed in claim 7, wherein:

after finishing the separated update sub-intervals for the master buffer block, the master buffer block is pushed into data blocks of the FLASH memory, the slave buffer block is changed to play the role of the master buffer block, and a spare block is selected from the blocks of the FLASH memory to play the role of the slave buffer block.