INSTRUCTIONS AND LOGIC TO PROVIDE GENERAL PURPOSE GF(256) SIMD CRYPTOGRAPHIC ARITHMETIC FUNCTIONALITY

• US 20150067302A1
• Filed: 06/26/2014
• Published: 03/05/2015
• Est. Priority Date: 12/28/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gueron, Shay
• Application Number:
  US14/316,511
• Publication Number:
  US 20150067302A1
• Time in Patent Office: Days
• US Class Current: 712/210
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms

Abstract

Instructions and logic provide general purpose GF(2⁸) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD binary finite field multiplicative inverse, the instruction specifying a source data operand, and an irreducible polynomial, to compute an inverse modulo the irreducible polynomial for each element of the source data operand. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix and the translation vector are applied to each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.

Claims

1. A processor comprising:

a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) binary finite field multiplicative inverse, the first instruction specifying a source data operand set, and a monic irreducible polynomial; and

one or more execution units, responsive to the decoded first instruction, to;

compute a SIMD binary finite-field multiplicative inverse modulo the irreducible polynomial for each element of the source data operand set; and

store a result of the first instruction in a SIMD destination register.

2. The processor of claim 1, wherein the first instruction specifies said SIMD destination register as a destination operand.

3. The processor of claim 1, wherein the first instruction specifies a SIMD register to hold 16 byte elements as the source data operand set.

4. The processor of claim 1, wherein the first instruction specifies a SIMD register to hold 32 byte elements as the source data operand set.

5. The processor of claim 1, wherein the first instruction specifies a SIMD register to hold 64 byte elements as the source data operand set.

6. The processor of claim 1, wherein computing the SIMD binary finite field multiplicative inverse is performed by raising each element of the source data operand set to the power 254 modulo the irreducible polynomial in the Galois field GF(2⁸).

7. The processor of claim 1, wherein the irreducible polynomial is specified in the first instruction mnemonic as 1B to indicate x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).

8. The processor of claim 2, wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value 1B to indicate x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).

9. The processor of claim 1, wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value F5 to indicate x⁸+x⁷+x⁶+x⁵+x⁴+x²+1 in the Galois field GF(2⁸).

10. A machine-readable medium to record functional descriptive material including one or more executable instructions, which if executed on behalf of a thread of a machine causes the machine to:

access a source data operand set of elements, and a monic irreducible polynomial;

computing a Single Instruction Multiple Data (SIMD) binary finite-field multiplicative inverse modulo the irreducible polynomial for each element of the source data operand set; and

store a result of the SIMD binary finite-field multiplicative inverse modulo the irreducible polynomial in a SIMD destination register.

11. The machine-readable medium of claim 10, wherein the irreducible polynomial is specified in an immediate operand of a first instruction as a hexadecimal control value 1B to indicate

x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).

12. The machine-readable medium of claim 10, wherein the irreducible polynomial is specified in a first instruction mnemonic as 1B to indicate x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).

13. A method comprising:

decoding a first instruction for a Single Instruction Multiple Data (SIMD) binary finite field multiplicative inverse, the first instruction specifying a source data operand set, and a monic irreducible polynomial;

computing a SIMD binary finite-field multiplicative inverse modulo the irreducible polynomial for each element of the source data operand set responsive to the decoded first instruction; and

storing a result of the first instruction in a SIMD destination register.

14. The method of claim 13, wherein the monic irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value 1B to indicate x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).

15. The method of claim 13, wherein the irreducible polynomial is specified in the first instruction mnemonic as 1B to indicate x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).

16. A processing system comprising:

a memory to store a first instruction for a SIMD secure hashing algorithm round slice; and

a processor comprising;

an instruction fetch stage to fetch the first instruction;

a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) binary finite field multiplicative inverse, the first instruction specifying a source data operand set, and a monic irreducible polynomial; and

one or more execution units, responsive to the decoded first instruction, to;

compute a SIMD binary finite-field multiplicative inverse modulo the irreducible polynomial for each element of the source data operand set; and

store a result of the first instruction in a SIMD destination register.

17. The processing system of claim 16, wherein the irreducible polynomial is specified in the first instruction mnemonic as 1B to indicate x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).

18. The processing system of claim 16, wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value 1B to indicate x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).

19. The processing system of claim 16, wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value 87 to indicate x¹²⁸+x⁷+x²+x+1 in the Galois field GF(2¹²⁸).

20. The processing system of claim 16, wherein the irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value F5 to indicate x⁸+x⁷+x⁶+x⁵+x⁴+x²+1 in the Galois field GF(2⁸).

21. The processing system of claim 16, wherein the first instruction is further for a SIMD affine transformation of each binary finite field multiplicative inverse, and said one or more execution units, responsive to the decoded first instruction, are further to:

perform a SIMD affine transformation by applying a transformation matrix operand to the multiplicative inverse of each element of the source data operand set, and applying a translation vector operand to each transformed multiplicative inverse of an element of the source data operand set to generate a result of the first instruction.

22. The processing system of claim 21, wherein the irreducible polynomial is specified in the first instruction mnemonic as 1B to indicate x⁸+x⁴+x³+x+1 in the Galois field GF(2⁸).