SPECIALIZED MEMORY DISAMBIGUATION MECHANISMS FOR DIFFERENT MEMORY READ ACCESS TYPES

• US 20150067305A1
• Filed: 08/30/2013
• Published: 03/05/2015
• Est. Priority Date: 08/30/2013
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Olson, Lena E., Eckert, Yasuko, Manne, Srilatha
• Granted Patent: US 9,524,164 B2
• Time in Patent Office: Days
• US Class Current: 712/225
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A system and method for efficient predicting and processing of memory access dependencies. A computing system includes control logic that marks a detected load instruction as a first type responsive to predicting the load instruction has high locality and is a candidate for store-to-load (STL) data forwarding. The control logic marks the detected load instruction as a second type responsive to predicting the load instruction has low locality and is not a candidate for STL data forwarding. The control logic processes a load instruction marked as the first type as if the load instruction is dependent on an older store operation. The control logic processes a load instruction marked as the second type as if the load instruction is independent on any older store operation.

Claims

1. A computing system comprising:

control logic configured to;

determine an instruction is a load instruction;

mark the load instruction as a first type in response to predicting a location in the memory accessed by the load instruction has read and write spatial and/or temporal locality that exceeds a threshold;

when marked as the first type, process the load instruction as if the load instruction is dependent on an older store instruction; and

when not marked as the first type, process the load instruction as if the load instruction is independent of any older store instruction.

2. The computing system as recited in claim 1, wherein said predicting comprises at least determining from address source operands whether the load instruction accesses a stack memory region in the memory.

3. The computing system as recited in claim 1, wherein the computing system further comprises a data cache, wherein the control logic is further configured to prevent access of the data cache for the load instruction marked as the first type.

4. The computing system as recited in claim 3, wherein the computing system further comprises a store buffer, wherein to determine said predicting is inaccurate, the control logic is further configured to determine at least the load instruction marked as the first type indexes into the store buffer with a corresponding load address and misses.

5. The computing system as recited in claim 4, wherein the load instruction marked as the first type indexes into the store buffer with a corresponding load address when each of the older outstanding store instructions has resolved a corresponding store address.

6. The computing system as recited in claim 1, wherein the computing system further comprises a store buffer, wherein the control logic is further configured to prevent access of the store buffer for the load instruction not marked as the first type.

7. The computing system as recited in claim 6, wherein the computing system further comprises a data cache, wherein to determine said predicting is inaccurate, the control logic is further configured to determine:

an outstanding store instruction older than the load instruction has a same address as the load instruction not marked as the first type; and

the load instruction not marked as the first type is indicated as having received data from the data cache.

8. The computing system as recited in claim 7, wherein the control logic is further configured to compare addresses of said store instruction and the load instruction not marked as the first type when said store instruction is ready to retire.

9. The computing system as recited in claim 1, wherein the computing system further comprises a data structure, wherein the control logic is further configured to:

mark the load instruction as a second type in response to predicting a location in the memory accessed by the load instruction has read and write spatial and/or temporal locality that does not exceed a threshold; and

store a program counter (PC) of the load instruction in the data structure in response to determining said predicting is inaccurate.

10. The computing system as recited in claim 9, wherein said predicting comprises at least accessing the data structure with a PC of a given load instruction, wherein when a hit occurs, the control logic is further configured to switch the marking of the load instruction from the first type to the second type, or vice-versa.

11. The computing system as recited in claim 1, wherein the computing system further comprises a data cache and a store buffer, wherein in response to determining said predicting is inaccurate, the control logic is further configured to perform at least one of:

send result data from the data cache, rather than the store buffer, to the load instruction marked as the first type; and

send result data from the store buffer, rather than the data cache, to the load instruction not marked as the first type.

12. A method executable by at least one processor, the method comprising:

determining an instruction is a load instruction;

marking the load instruction as a first type in response to predicting a location in the memory accessed by the load instruction has read and write spatial and/or temporal locality that exceeds a threshold;

when marked as the first type, processing the load instruction as if the load instruction is dependent on an older store instruction; and

when not marked as the first type, processing the load instruction as if the load instruction is independent of any older store instruction.

13. The method as recited in claim 12, wherein said predicting comprises at least determining from address source operands whether the load instruction accesses a stack memory region in the memory.

14. The method as recited in claim 12, further comprising preventing access of a data cache for the load instruction marked as the first type.

15. The method as recited in claim 12, further comprising preventing access of a store buffer for the load instruction not marked as the first type.

16. The method as recited in claim 12, wherein in response to determining said predicting is inaccurate, the method further comprises performing at least one of:

sending result data from the data cache, rather than the store buffer, to the load instruction marked as the first type; and

sending result data from the store buffer, rather than the data cache, to the load instruction not marked as the first type.

17. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable to:

determine an instruction is a load instruction;

mark the load instruction as a first type in response to predicting a location in the memory accessed by the load instruction has read and write spatial and/or temporal locality that exceeds a threshold;

when marked as the first type, process the load instruction as if the load instruction is dependent on an older store instruction; and

when not marked as the first type, process the load instruction as if the load instruction is independent of any older store instruction.

18. The non-transitory computer readable storage medium as recited in claim 17, wherein said predicting comprises at least determining from address source operands whether the load instruction accesses a stack memory region in the memory.

19. The non-transitory computer readable storage medium as recited in claim 17, wherein the program instructions are further executable to prevent access of a data cache for the load instruction marked as the first type.

20. The non-transitory computer readable storage medium as recited in claim 17, wherein the program instructions are further executable to prevent access of a store buffer for the load instruction not marked as the first type.