MEMORY CONTROLLER

• US 20150067439A1
• Filed: 03/12/2014
• Published: 03/05/2015
• Est. Priority Date: 09/03/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: YAMAKI, Ryo, Takeda, Naomi
• Granted Patent: US 9,424,126 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence

Abstract

According to one embodiment, a memory controller according to the embodiments includes an encoder that sequentially calculates parity based on data; a parity buffer that stores completed parity and intermediate parity based on data less than a predetermined size; a write processing unit that writes data and completed parity on a non-volatile memory; a decoder; and a controller that performs a decoding process based on the data read from the non-volatile memory and the intermediate parity in the parity buffer, when receiving a read request to inputted data in a stage in which the a number of inputted data to the encoder is less than the predetermined size.

Claims

1. A memory controller that controls a non-volatile memory, the memory controller comprising:

an encoder configured to sequentially receive data, and to sequentially calculate parity based on the data,

a buffer configured to store the parity calculated by the encoder, the parity stored in the buffer including at least one of completed parity calculated based on the data having predetermined size and intermediate parity calculated based on the data having size less than the predetermined size;

a write processing unit configured to write the data and the completed parity to a non-volatile memory;

a decoder configured to perform a decoding process based on the data and the parity; and

a controller configured to control the decoder to perform decoding based on the data read from the non-volatile memory and the intermediate parity stored in the buffer when receiving a read request directing to the data for which the intermediate parity in the buffer being generated.

2. The memory controller according to claim 1, wherein the write processing unit writes the data on the non-volatile memory in parallel with the calculation of the parity based on the data in the encoder.

3. The memory controller according to claim 1, further comprising:

a data buffer configured to store the data, wherein,

when the controller receives a read request for the data inputted to the encoder in a state in which only data having size less than the predetermined size is inputted to the encoder, the controller writes zero in a region corresponding to data that is not yet written on the non-volatile memory out of a region allocated to the data having predetermined size, on the data buffer.

4. The memory controller according to claim 3, wherein

the encoder is specified as a first encoder, and the parity is specified as first parity;

and

the memory controller further includes a second encoder configured to generate second parity using unit data that is data having size less than write unit data,

the write unit data includes the unit data and the second parity.

5. The memory controller according to claim 1, wherein

the memory controller performs writing to the non-volatile memory for each write unit data with a predetermined data amount, and

the predetermined size of the data includes the plural write unit data.

6. The memory controller according to claim 1, wherein the write processing unit writes the intermediate parity on the non-volatile memory, when a predetermined command is received in a state in which only data having size less than the predetermined size inputted to the encoder.

7. The memory controller according to claim 1, wherein, when writing is not performed on a part of a region, which is specified as an unwritten region, in the non-volatile memory into which the data having predetermined size is to be written, the encoder calculates the parity using zero as input data instead of the data corresponding to the unwritten region.

8. A memory controller that controls a non-volatile memory, the memory controller comprising:

an encoder configured to sequentially receive data, and to sequentially calculate parity based on the data sequentially inputted,

a parity buffer configured to store the parity calculated by the encoder, the parity stored in the parity buffer including at least either one of completed parity calculated based on predetermined size of the data, and intermediate parity calculated based on the data having size less than the predetermined size; and

a write processing unit configured to write the data and the completed parity to a non-volatile memory, wherein

the write processing unit writes the intermediate parity on the non-volatile memory, when receiving a predetermined command in a stage in which the size of the data inputted to the encoder is less than the predetermined size.

9. The memory controller according to claim 8, wherein, when new data is written after the intermediate parity is written on the non-volatile memory, the write processing unit reads the intermediate parity from the non-volatile memory, and the encoder calculates the parity using the intermediate parity read from the non-volatile memory and the new data.

10. The memory controller according to claim 8, further comprising:

a decoder configured to perform a decoding process using the parity and the data.

11. The memory controller according to claim 8, wherein, when writing is not performed on a part of a region, which is specified as an unwritten region, in the non-volatile memory into which the data having predetermined size is to be written, the encoder calculates the parity using zero as input data instead of the data corresponding to the unwritten region.

12. A memory controller that controls a non-volatile memory, the memory controller comprising:

an encoder configured to sequentially receive data, and to sequentially calculate parity based on the data sequentially inputted; and

a write processing unit configured to write the data and the parity to a non-volatile memory, wherein when writing is not performed on a part of a region, which is specified as an unwritten region, in the non-volatile memory into which the data having predetermined size is to be written, the encoder calculates the parity using zero as input data instead of the data corresponding to the unwritten region.

13. The memory controller according to claim 12, further comprising:

a decoder configured to perform a decoding process using the parity and the data.