FLASH SUBSYSTEM ORGANIZED INTO PAIRS OF UPPER AND LOWER PAGE LOCATIONS

• US 20150067449A1
• Filed: 11/11/2014
• Published: 03/05/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Nemazie, Siamack, Mandapuram, Anilkumar
• Granted Patent: US 9,158,623 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes

Abstract

A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

Claims

1. A memory system comprising:

a flash subsystem organized into pairs of upper and lower page locations, an upper and lower page location pair for saving a page of data; and

a flash controller coupled to the flash subsystem and responsive to a page of data made of a pair of upper page and lower page, the flash controller operable to generate split segments from the upper page and the lower page pair, the split segments each including split data, the flash controller further operable to compute redundancy associated with the split data and to program the split data of the upper page into an upper page location and a corresponding split data of the lower page into a lower page location, the flash controller further operable to program the computed redundancy into the upper page location or the lower page location.

2. The memory system, as recited in claim 1, wherein the flash controller is configured to write pages in sequential order.

3. The memory system, as recited in claim 1, further including a buffer coupled to the flash controller and made of flash-backed memory.

4. The memory system, as recited in claim 1, further including a buffer coupled to the flash controller wherein the buffer includes magnetic random access memory (MRAM).

5. The memory system, as recited in claim 4, wherein the magnetic random access memory (MRAM) is spin transfer torque magnetic random access memory (STTMRAM).

6. The memory system, as recited in claim 1, wherein the flash subsystem includes more than one flash die and is organized into blocks and a first block is in a first flash die and a second block is in a second flash die, further wherein the lower page of data is in the first block and the upper page of data is in the second block, the lower page of data of the first block paired with the upper page of data of the second block thereby causing substantially concurrent reading of the lower page of data or the upper of data.

7. The memory system, as recited in claim 6, wherein the first flash die and the second flash die are coupled to different flash channels.

8. The memory system, as recited in claim 1, wherein the redundancy is part of an error correction code (ECC) using Bose, Chaudhuri, and Hocquenghem (BCH) code.

9. The memory system, as recited in claim 8, wherein the ECC is a low-density parity-check (LDPC) code.

10. The memory system, as recited in claim 1, wherein the flash subsystem is organized into blocks.

11. A memory system comprising:

a flash subsystem responsive to pages to be programmed therein, the pages organized into upper pages and lower pages, the upper pages being saved in upper page locations of the flash subsystem and the lower pages being saved in lower page locations of the flash system, each of the upper pages and lower pages including a plurality of segments having data, each segment being split into split segments with split data; and

a flash controller coupled to the flash subsystem, the flash controller responsive to a page made of an upper page and a lower page, the flash controller being operable to generate split segments from the upper pages and the lower pages and to compute redundancy associated with split upper and lower segments, the flash controller being operable to program the split data of the upper page and a corresponding split data of the lower page or the computed redundancy into an upper page location or a lower page location of the flash subsystem.

12. The memory system, as recited in claim 11, wherein the flash controller is configured to write pages in sequential order.

13. The memory system, as recited in claim 11, further including a buffer coupled to the flash controller and made of flash-backed memory.

14. The memory system, as recited in claim 11, further including a buffer coupled to the flash controller wherein the buffer includes magnetic random access memory (MRAM).

15. The memory system, as recited in claim 14, wherein the magnetic random access memory (MRAM) is spin transfer torque magnetic random access memory (STTMRAM).

16. The memory system, as recited in claim 11, wherein the flash subsystem includes more than one flash die and is organized into blocks and a first block is in a first flash die and a second block is in a second flash die, further wherein the lower page of data is in the first block and the upper page of data is in the second block, the lower page of data of the first block paired with the upper page of data of the second block thereby causing substantially concurrent reading of the lower page of data or the upper of data.

17. The memory system, as recited in claim 16, wherein the first flash die and the second flash die are coupled to different flash channels.

18. The memory system, as recited in claim 11, wherein the redundancy is part of an error correction code (ECC) using Bose, Chaudhuri, and Hocquenghem (BCH) code.

19. The memory system, as recited in claim 18, wherein the ECC is a low-density parity-check (LDPC) code.

20. The memory system, as recited in claim 11, wherein the flash subsystem is organized into blocks.

21. A memory system comprising:

a flash subsystem configured to save pages of information, each page of information including one or more codewords, each codeword having data and ECC, each of the pages of information having an upper page and a lower page, the flash subsystem configured to save upper pages in upper page locations and to save lower pages in lower page locations; and

a flash controller coupled to the flash subsystem and operable to save pages of information in the flash subsystem, the flash controller operable to save a page of information having a codeword with data and ECC,

wherein the codeword is split between an upper page location and a lower page location of the flash subsystem.

22. The memory system, as recited in claim 21, wherein the flash controller is configured to write pages in sequential order.

23. The memory system, as recited in claim 21, further including a buffer coupled to the flash controller and made of flash-backed memory.

24. The memory system, as recited in claim 21, further including a buffer coupled to the flash controller wherein the buffer includes magnetic random access memory (MRAM).

25. The memory system, as recited in claim 24, wherein the magnetic random access memory (MRAM) is spin transfer torque magnetic random access memory (STTMRAM).

26. The memory system, as recited in claim 21, wherein the flash subsystem includes more than one flash die and is organized into blocks and a first block is in a first flash die and a second block is in a second flash die, further wherein the lower page of data is in the first block and the upper page of data is in the second block, the lower page of data of the first block paired with the upper page of data of the second block thereby causing substantially concurrent reading of the lower page of data or the upper of data.

27. The memory system, as recited in claim 26, wherein the first flash die and the second flash die are coupled to different flash channels.

28. The memory system, as recited in claim 21, wherein the redundancy is part of an error correction code (ECC) using Bose, Chaudhuri, and Hocquenghem (BCH) code.

29. The memory system, as recited in claim 28, wherein the ECC is a low-density parity-check (LDPC) code.

30. The memory system, as recited in claim 21, wherein the flash subsystem is organized into blocks.

31. A memory system comprising:

a flash subsystem organized into upper page locations and lower page locations, the upper page locations configured to save first segments and the lower page locations configured to save second segments, the first and second segments including split data and ECC and forming at least a part of a page; and

a flash controller coupled to the flash subsystem and operable to save a page in the flash subsystem, the page having a first segment and a second segment with split data and ECC, the flash controller operable to save the first segment into an upper page location of the flash subsystem and the second segment into a lower page location of the flash subsystem.

32. The memory system, as recited in claim 31, wherein the flash controller is configured to write pages in sequential order.

33. The memory system, as recited in claim 31, further including a buffer coupled to the flash controller and made of flash-backed memory.

34. The memory system, as recited in claim 31, further including a buffer coupled to the flash controller wherein the buffer includes magnetic random access memory (MRAM).

35. The memory system, as recited in claim 34, wherein the magnetic random access memory (MRAM) is spin transfer torque magnetic random access memory (STTMRAM).

36. The memory system, as recited in claim 31, wherein the flash subsystem includes more than one flash die and is organized into blocks and a first block is in a first flash die and a second block is in a second flash die, further wherein the lower page of data is in the first block and the upper page of data is in the second block, the lower page of data of the first block paired with the upper page of data of the second block thereby causing substantially concurrent reading of the lower page of data or the upper of data.

37. The memory system, as recited in claim 36, wherein the first flash die and the second flash die are coupled to different flash channels.

38. The memory system, as recited in claim 31, wherein the redundancy is part of an error correction code (ECC) using Bose, Chaudhuri, and Hocquenghem (BCH) code.

39. The memory system, as recited in claim 38, wherein the ECC is a low-density parity-check (LDPC) code.

40. The memory system, as recited in claim 31, wherein the flash subsystem is organized into blocks.