FLASH SUBSYSTEM ORGANIZED INTO PAIRS OF UPPER AND LOWER PAGE LOCATIONS
First Claim
Patent Images
1. A memory system comprising:
- a flash subsystem organized into pairs of upper and lower page locations, an upper and lower page location pair for saving a page of data; and
a flash controller coupled to the flash subsystem and responsive to a page of data made of a pair of upper page and lower page, the flash controller operable to generate split segments from the upper page and the lower page pair, the split segments each including split data, the flash controller further operable to compute redundancy associated with the split data and to program the split data of the upper page into an upper page location and a corresponding split data of the lower page into a lower page location, the flash controller further operable to program the computed redundancy into the upper page location or the lower page location.
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Abstract
A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.
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Citations
40 Claims
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1. A memory system comprising:
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a flash subsystem organized into pairs of upper and lower page locations, an upper and lower page location pair for saving a page of data; and a flash controller coupled to the flash subsystem and responsive to a page of data made of a pair of upper page and lower page, the flash controller operable to generate split segments from the upper page and the lower page pair, the split segments each including split data, the flash controller further operable to compute redundancy associated with the split data and to program the split data of the upper page into an upper page location and a corresponding split data of the lower page into a lower page location, the flash controller further operable to program the computed redundancy into the upper page location or the lower page location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory system comprising:
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a flash subsystem responsive to pages to be programmed therein, the pages organized into upper pages and lower pages, the upper pages being saved in upper page locations of the flash subsystem and the lower pages being saved in lower page locations of the flash system, each of the upper pages and lower pages including a plurality of segments having data, each segment being split into split segments with split data; and a flash controller coupled to the flash subsystem, the flash controller responsive to a page made of an upper page and a lower page, the flash controller being operable to generate split segments from the upper pages and the lower pages and to compute redundancy associated with split upper and lower segments, the flash controller being operable to program the split data of the upper page and a corresponding split data of the lower page or the computed redundancy into an upper page location or a lower page location of the flash subsystem. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A memory system comprising:
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a flash subsystem configured to save pages of information, each page of information including one or more codewords, each codeword having data and ECC, each of the pages of information having an upper page and a lower page, the flash subsystem configured to save upper pages in upper page locations and to save lower pages in lower page locations; and a flash controller coupled to the flash subsystem and operable to save pages of information in the flash subsystem, the flash controller operable to save a page of information having a codeword with data and ECC, wherein the codeword is split between an upper page location and a lower page location of the flash subsystem. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A memory system comprising:
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a flash subsystem organized into upper page locations and lower page locations, the upper page locations configured to save first segments and the lower page locations configured to save second segments, the first and second segments including split data and ECC and forming at least a part of a page; and a flash controller coupled to the flash subsystem and operable to save a page in the flash subsystem, the page having a first segment and a second segment with split data and ECC, the flash controller operable to save the first segment into an upper page location of the flash subsystem and the second segment into a lower page location of the flash subsystem. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40)
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Specification