CELL LAYOUT DESIGN AND METHOD

• US 20150067616A1
• Filed: 08/28/2013
• Published: 03/05/2015
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HSU, Chin-Hsiung, HOU, Yuan-Te, TIEN, Li-Chun, ZHUANG, Hui-Zhong, FAN, Fang-Yu, CHEN, Wen-Hao, CHEN, Ting Yu
• Granted Patent: US 9,087,170 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Claims

1. A method, comprising:

dividing a plurality of cells into groups such that each cell in a group includes a common attribute pertaining to a location of one or more boundary pins within the cell;

selecting the one or more groups of cells that meet at least one selection guideline that identifies suitable positions for boundary pins within a cell; and

storing the cells of the one or more groups of cells that meet the selection guideline in a non-transient computer readable storage medium to create a cell library,

wherein at least one of the dividing, selecting, and storing is performed using a processor.

2. The method of claim 1, further comprising:

determining if an initial layout of cells includes a pin access problem, wherein the initial layout of cells includes an arrangement of two or more cells selected from the cell library;

if the initial layout includes at least one pin access problem, then adjusting at least one cell of the initial layout to produce a second layout that differs from the initial layout; and

storing one of the initial layout and the second layout as a final layout.

3. The method of claim 2, further comprising:

fabricating at least one photolithography mask based on the final layout; and

fabricating an integrated circuit using the at least one photolithography mask.

4. The method of claim 2, wherein adjusting at least one cell of the initial layout includes flipping at least one cell of the at least one cell.

5. The method of claim 2, wherein determining if the initial layout of cells includes a pin access problem includes determining if a marker of a first cell overlaps a marker of a second cell.

6. The method of claim 2, wherein, if the initial layout includes a pin access problem, the method includes analyzing the initial layout using dynamic programming to identify a solution to the pin access problem.

7. The method of claim 1, further comprising:

for each cell of the cells in the cell library, adding a marker identifying a location of a pin or the absence of a pin to at least one layer of the cell.

8. A system, comprising:

a non-transient computer readable storage medium; and

a processor in signal communication with the non-transient computer readable storage medium, the processor configured to;

divide a plurality of cells into groups such that each cell in a group includes a common attribute pertaining to a location of one or more boundary pins within the cell;

select the one or more groups of cells that meet at least one selection guidelines that identifies suitable positions for boundary pins within a cell to create a cell library;

determine if a first layout of cells includes a pin access problem, wherein the first layout of cells includes an arrangement of at least two or more cells selected from the cell library; and

adjust at least one cell of the first layout to produce a second layout that differs from the first layout if the first layout includes at least one pin access problem.

9. The system of claim 8, wherein the processor is configured to:

determine if a cell meets the selection guideline; and

store the cell in the cell library in the non-transient computer readable storage medium if the cell meets the selection guideline.

10. The system of claim 9, wherein the processor is configured to

for each cell that meets the selection guideline, add a marker identifying a location of a pin or the absence of a pin to at least one layer of the cell.

11. The system of claim 8, wherein the processor is configured to flip at least one cell when the processor adjusts at least one cell of the first layout.

12. The system of claim 8, wherein the processor is configured to determine if a marker of a first cell overlaps a marker of a second cell when determining if the first layout of cells includes a pin access problem.

13. The system of claim 8, wherein the selection guideline identifies a suitable position of a boundary pin within a cell.

14. A non-transient computer readable storage medium encoded with program code, wherein when the program code is executed by a processor, the processor performs a method, the method comprising:

dividing a plurality of cells into groups such that each cell in a group includes a common attribute pertaining to a location of one or more boundary pins within the cell;

creating a cell library by selecting the one or more groups of cells that meet a selection guideline that identifies suitable positions for boundary fins within a cell;

determining if a first layout of cells includes a pin access problem, wherein the first layout includes an arrangement of at least two cells selected from the cell library;

if the first layout includes at least one pin access problem, then adjusting at least one cell of the first layout to produce a second layout that differs from the first layout; and

storing one of the first layout and the second layout as a final layout.

15. The non-transient computer readable storage medium of claim 14, wherein the method includes comparing one or more cells against the selection guideline;

and

determining if the one or more cells meet the selection guideline.

16. The non-transient computer readable storage medium of claim 15, wherein the method includes:

for each of the cells that meet the selection guideline, adding a marker to identify the presence of a pin in an area or the absence of a pin in an area to at least one layer of the cell.

17. The non-transient computer readable storage medium of claim 16, wherein the marker includes a portion that extends beyond a boundary of the cell to identify a location of a pin and includes a portion that extends inwardly from the boundary of the cell to identify the absence of a pin in an area.

18. The non-transient computer readable storage medium of claim 14, wherein adjusting at least one cell of the first layout includes flipping at least one cell of the at least one cell.

19. The non-transient computer readable storage medium of claim 14, wherein determining if a first layout of cells includes a pin access problem includes determining if a marker of a first cell overlaps a marker of a second cell.

20. The non-transient computer readable storage medium of claim 14, wherein the selection guideline identifies a suitable position of a boundary pin within a cell.