TRANSISTOR FABRICATION TECHNIQUE INCLUDING SACRIFICIAL PROTECTIVE LAYER FOR SOURCE/DRAIN AT CONTACT LOCATION

• US 20150069473A1
• Filed: 09/06/2013
• Published: 03/12/2015
• Est. Priority Date: 09/06/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Glass, Glenn A., Murthy, Anand S., Jackson, Michael J., Hattendorf, Michael L., Joshi, Subhash M.
• Granted Patent: US 9,633,835 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).

Claims

1. A semiconductor device, comprising:

a substrate having a number of channel regions;

source/drain regions on the substrate and adjacent to a corresponding channel region;

a gate region above each channel region and between the source/drain regions;

a sacrificial protective layer on a portion of the source/drain regions;

at least one insulator layer over the sacrificial protective layer;

trench contact areas in the source/drain regions, wherein the sacrificial protective layer is absent from the trench contact areas; and

at least one contact layer in the trench contact areas of the source/drain regions.

2. The device of claim 1 wherein the sacrificial protective layer material is germanium (Ge).

3. The device of claim 1 wherein the sacrificial protective layer material includes at least one of titanium (Ti), cobalt (Co), and aluminum oxide (Al₂O₃).

4. The device of claim 1 wherein the sacrificial protective layer material includes at least one of boron nitride (BN) and spin-on carbon hardmask (CHM).

5. The device of claim 1 wherein the sacrificial protective layer material has an etch rate that is at least 3×

greater than the corresponding etch rate of the at least one insulator layer and S/D regions, for a given etch chemistry.

6. The device of claim 1 wherein the sacrificial protective layer material has an etch rate that is at least 10×

greater than the corresponding etch rate of the at least one insulator layer and S/D regions, for a given etch chemistry.

7. The device of claim 1 wherein the sacrificial protective layer material has a high etch rate in chemistry that does not remove more than 15% of thickness of the source/drain regions or the at least one insulator layer.

8. The device of claim 1 wherein the sacrificial protective layer is less than 100 angstroms thick.

9. The device of claim 1 wherein each gate region includes a gate stack configured with a gate electrode and a gate dielectric between the gate electrode and a corresponding channel region.

10. The device of claim 1 wherein the at least one insulator layer comprises a silicon compound.

11. The device of claim 1 wherein the device is a planar transistor.

12. The device of claim 1 wherein the device is a non-planar transistor.

13. The device of claim 12 wherein the source/drain regions are implemented in a fin structure having opposing sidewalls and a top, and the at least one insulator layer is not on the sidewalls of the fin.

14. A mobile computing system comprising the device of claim 1.

15. A semiconductor device, comprising:

a fin on a substrate, the fin comprising a semiconductor material and having a channel region and corresponding source/drain regions adjacent thereto;

a gate region above the channel region and between the source/drain regions;

a sacrificial protective layer on a portion of the source/drain regions;

at least one insulator layer over the sacrificial protective layer;

trench contact areas in the source/drain regions, wherein the sacrificial protective layer is absent from the trench contact areas; and

at least one contact layer in the trench contact areas of the source/drain regions.

16. The device of claim 15 wherein the sacrificial protective layer material includes at least one of germanium (Ge), titanium (Ti), cobalt (Co), aluminum oxide (Al₂O₃), boron nitride (BN), and spin-on carbon hardmask (CHM).

17. A method for forming a semiconductor device, comprising:

depositing a sacrificial protective layer on at least a portion of source/drain regions provisioned on a substrate adjacent to a corresponding channel region;

depositing at least one insulator layer over the sacrificial protective layer;

performing a first etch to form source/drain contact trenches;

performing a selective etch to remove the sacrificial protective layer from the source/drain contact trenches; and

depositing at least one contact layer in the source/drain contact trenches.

18. The method of claim 17 wherein the sacrificial protective layer material includes germanium (Ge).

19. The method of claim 18 wherein the selective etch includes using at least one of ozonated water, peroxide, sulfuric acid, nitric acid, and ash processing.

20. The method of claim 17 wherein the sacrificial protective layer material includes at least one of titanium (Ti), cobalt (Co), and aluminum oxide (Al₂O₃).

21. The method of claim 20 wherein the selective etch includes using a strong sulfuric acid.

22. The method of claim 17 wherein the sacrificial protective layer material includes at least one of boron nitride (BN) and spin-on carbon hardmask (CHM).

23. The method of claim 22 wherein the selective etch includes an ash process that may or may not be followed by an optional sulfuric clean.

24. The method of claim 17 wherein the sacrificial protective layer is selectively deposited on at least a portion of source/drain surfaces and not on insulator surfaces.

25. The method of claim 17 wherein the sacrificial protective layer is non-selectively deposited on all surfaces.