SEMICONDUCTOR DEVICE WITH REDUCED ELECTRICAL RESISTANCE AND CAPACITANCE

• US 20150069475A1
• Filed: 09/12/2013
• Published: 03/12/2015
• Est. Priority Date: 09/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Ching, Kuo-Cheng, Guo, Ta-Pen, Diaz, Carlos H.
• Granted Patent: US 10,008,566 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

Claims

1. A semiconductor device comprising:

a first type region comprising a first conductivity type;

a second type region comprising a second conductivity type;

a channel region extending between the first type region and the second type region, the channel region separated a first distance from a first portion of the first type region; and

a gate region surrounding the channel region, a first portion of the gate region separated a second distance from the first portion of the first type region, wherein the second distance is greater than the first distance.

2. The semiconductor device of claim 1, wherein a second portion of the gate region is separated a third distance from the first portion of the first type region.

3. The semiconductor device of claim 2, wherein a first portion of a first insulator layer surrounds a second drift region below the channel region and extends between the first portion of the first type region and the second portion of the gate region.

4. The semiconductor device of claim 1, wherein the first distance is between about 0 nm to about 1 nm.

5. The semiconductor device of claim 1, wherein a gate region length of the gate region is greater than a channel region length of the channel region.

6. The semiconductor device of claim 1, wherein a first portion of a second insulator layer surrounds the channel region and extends between the channel region and a metal layer of the gate region.

7. The semiconductor device of claim 1, wherein the channel region is comprised within a vertical nanowire.

8. The semiconductor device of claim 1, wherein the first type region comprises a source region and the second type region comprises a drain region.

9. The semiconductor device of claim 1, wherein the first type region comprises a drain region and the second type region comprises a source region.

10. A semiconductor device comprising:

a first type region comprising a first conductivity type;

a second type region comprising a second conductivity type;

a channel region extending between the first type region and the second type region, the channel region separated a first distance from a first portion of the first type region; and

a gate region surrounding the channel region, a first portion of the gate region separated a second distance from the first portion of the first type region, wherein the second distance is greater than the first distance; and

a first portion of a first insulator layer surrounding a second drift region below the channel region and extending between the first portion of the first type region and a second portion of the gate region.

11. The semiconductor device of claim 10, wherein the first distance is between about 0 nm to about 1 nm.

12. The semiconductor device of claim 10, wherein the first conductivity type of the first type region is the same as the second conductivity type of the second type region.

13. The semiconductor device of claim 10, wherein a gate region length of the gate region is greater than a channel region length of the channel region.

14. The semiconductor device of claim 10, wherein a first portion of a second insulator layer surrounds the channel region and extends between the channel region and a metal layer of the gate region.

15. The semiconductor device of claim 10, wherein the channel region is comprised within a vertical nanowire.

16. The semiconductor device of claim 10, wherein the first type region comprises a source region and the second type region comprises a drain region.

17. The semiconductor device of claim 10, wherein the first type region comprises a drain region and the second type region comprises a source region.

18. A method of forming a semiconductor device, the method comprising:

forming a first type region comprising a first conductivity type;

forming a second type region comprising a second conductivity type;

forming a channel region extending between the first type region and the second type region, the channel region separated a first distance from a first portion of the first type region; and

forming a gate region surrounding the channel region, a first portion of the gate region separated a second distance from the first portion of the first type region, wherein the second distance is greater than the first distance.

19. The method of claim 18, comprising forming a first portion of a first insulator layer surrounding a second drift region below the channel region and extending between the first type region and a second portion of the gate region.

20. The method of claim 19, comprising forming a spacer surrounding the channel region and over the first portion of the first insulator layer.