Method of Forming Different Voltage Devices with High-K Metal Gate
First Claim
1. A semiconductor fabrication process comprising:
- providing a wafer comprising a first device area for forming one or more first voltage level transistors, a second device area for forming one or more second voltage level dual gate oxide transistors, and a third device area for forming one or more third voltage level transistors;
forming a high voltage gate dielectric stack on the first and third device areas of the wafer and not on the second device area of the wafer;
forming a dual gate oxide layer over the first, second, and third device areas of the wafer by depositing one or more oxide layers on the high voltage gate dielectric stack and on the exposed second device area of the wafer;
removing the high voltage gate dielectric stack and dual gate oxide layer from the third device area of the wafer while leaving the dual gate oxide layer formed on the first and second device areas;
forming a high-k gate dielectric stack over the first, second, and third device areas of the wafer to cover the dual gate oxide layer formed on the first and second device areas and the third device area of the wafer; and
forming a plurality of patterned high-k metal gate electrodes on the high-k gate dielectric stack in each of the first, second, and third device areas;
where the first voltage level is higher than the second voltage level which is higher than the third voltage level.
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Abstract
A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124), an upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each DGO transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers.
50 Citations
20 Claims
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1. A semiconductor fabrication process comprising:
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providing a wafer comprising a first device area for forming one or more first voltage level transistors, a second device area for forming one or more second voltage level dual gate oxide transistors, and a third device area for forming one or more third voltage level transistors; forming a high voltage gate dielectric stack on the first and third device areas of the wafer and not on the second device area of the wafer; forming a dual gate oxide layer over the first, second, and third device areas of the wafer by depositing one or more oxide layers on the high voltage gate dielectric stack and on the exposed second device area of the wafer; removing the high voltage gate dielectric stack and dual gate oxide layer from the third device area of the wafer while leaving the dual gate oxide layer formed on the first and second device areas; forming a high-k gate dielectric stack over the first, second, and third device areas of the wafer to cover the dual gate oxide layer formed on the first and second device areas and the third device area of the wafer; and forming a plurality of patterned high-k metal gate electrodes on the high-k gate dielectric stack in each of the first, second, and third device areas;
where the first voltage level is higher than the second voltage level which is higher than the third voltage level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a plurality of gate electrode structures on a shared substrate comprising:
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forming a first gate dielectric device in a first region of a semiconductor substrate for one or more first voltage level transistors, wherein the first gate dielectric device comprises a grown gate dielectric layer formed on the shared substrate, a deposited gate dielectric layer formed on the grown gate dielectric layer, a first high-k gate dielectric layer deposited on the deposited gate dielectric layer, and a second high-k gate dielectric layer deposited on the first high-k gate dielectric layer; forming a second gate dielectric device in a second region of a semiconductor substrate for one or more second voltage level transistors, wherein the second gate dielectric device comprises the first high-k gate dielectric layer deposited on the shared substrate, and the second high-k gate dielectric layer deposited on the first high-k gate dielectric layer; forming a third gate dielectric device in a third region of a semiconductor substrate for one or more third voltage level transistors, wherein the third gate dielectric device comprises a base gate dielectric layer grown on the third region of the shared substrate and a second high-k gate dielectric layer deposited on the base gate dielectric layer; forming one or more gate conductor layers on the first, second, and third gate dielectric devices; and selectively etching the gate conductor layers and the first, second, and third gate dielectric devices to form a plurality of gate electrode structures on the first, second, and third regions of the shared substrate; where the first gate dielectric device has a combined thickness that is thicker than the second gate dielectric device, where the second gate dielectric device has a combined thickness that is thicker than the first gate dielectric device, and where the first voltage level is higher than the second voltage level which is higher than the third voltage level. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor device having a plurality of transistors having different gate dielectric structures integrated on a shared substrate, comprising:
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a semiconductor substrate comprising a first device area for forming one or more first voltage level transistors, a second device area for forming one or more second voltage level dual gate oxide transistors, and a third device area for forming one or more third voltage level transistors; one or more first voltage level high-k metal gate transistors formed in the first device area, each comprising one or more patterned metal gate layers formed over a patterned first gate dielectric device comprising a grown oxide layer formed on the first region of the semiconductor substrate, a deposited gate oxide layer formed on the grown oxide layer, a first dual gate oxide layer deposited on the deposited gate oxide layer, and a first high-k gate dielectric layer deposited on the first dual gate oxide layer; one or more second voltage level high-k metal gate transistors formed in the second device area, each comprising one or more patterned metal gate layers formed over a patterned second gate dielectric device comprising a second dual gate oxide layer deposited on the second region of the semiconductor substrate and a second high-k gate dielectric layer deposited on the second dual gate oxide layer; and one or more third voltage level high-k metal gate transistors formed in the third device area, each comprising one or more patterned metal gate layers formed over a patterned third gate dielectric device comprising a base oxide layer grown on the third region of the semiconductor substrate and a third high-k gate dielectric layer deposited on the base oxide layer;
where the first voltage level is higher than the second voltage level which is higher than the third voltage level.
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Specification