SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK

• US 20150069535A1
• Filed: 09/12/2013
• Published: 03/12/2015
• Est. Priority Date: 09/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Chen, Chang-Yin, Chen, Yi - Jen, Chang, Yung Jung
• Granted Patent: US 9,520,474 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Claims

1. A semiconductor device, comprising:

a metal gate stack comprising a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric, the metal gate electrode comprising a first top surface and a second bottom surface substantially diametrically opposite the first top surface, the first top surface comprising a first surface length and the second bottom surface comprising a second surface length, wherein the first surface length is larger than the second surface length.

2. The semiconductor device of claim 1, wherein the metal gate electrode comprises a third surface and a fourth surface substantially diametrically opposite the third surface.

3. The semiconductor device of claim 2, wherein the second bottom surface is at a first angle with respect to the third surface that is greater than about 90 degrees and a second angle with respect to the fourth surface that is greater than about 90 degrees.

4. The semiconductor device of claim 2, wherein the first top surface is at a third angle with respect to the third surface that is less than about 90 degrees and a fourth angle with respect to the fourth surface that is less than about 90 degrees.

5. The semiconductor device of claim 2, wherein the third surface is not parallel with respect to the fourth surface.

6. A method of forming a semiconductor device, comprising:

forming a gate dielectric;

forming a silicon dummy layer over the gate dielectric such that a top surface of the silicon dummy layer is substantially diametrically opposite a bottom surface of the silicon dummy layer, and such that a top surface length of the top surface is not equal to a bottom surface length of the bottom surface; and

replacing the silicon dummy layer with a high-k metal gate electrode.

7. The method of claim 6, comprising etching through a photoresist layer before forming the gate dielectric.

8. The method of claim 7, comprising removing a BARC layer after etching through the photoresist layer.

9. The method of claim 8, comprising removing a bottom layer after removing the BARC layer.

10. The method of claim 6, comprising forming the silicon dummy layer such that the top surface length of the top surface is larger than the bottom surface length of the bottom surface.

11. The method of claim 10, comprising replacing the silicon dummy layer with the high-k metal gate electrode such that the high-k metal gate electrode comprises a first top surface and a second bottom surface substantially diametrically opposite the first top surface.

12. The method of claim 11, comprising replacing the silicon dummy layer with the high-k metal gate electrode such that the first top surface comprises a first surface length and the second bottom surface comprises a second surface length, and such that the first surface length is larger than the second surface length.

13. The method of claim 6, comprising forming a cap layer over the gate dielectric.

14. A method of forming a semiconductor device, comprising:

forming a silicon dummy layer over a substrate such that a top surface of the silicon dummy layer is substantially diametrically opposite a bottom surface of the silicon dummy layer, and such that a top surface length of the top surface is not equal to a bottom surface length of the bottom surface;

forming spacers on a first side and a second side of the silicon dummy layer;

removing the silicon dummy layer to define an opening between the spacers such that a top opening length of the opening is not equal to a bottom opening length of the opening;

forming a gate dielectric within the opening between the spacers over the substrate; and

forming a high-k metal gate electrode over the gate dielectric between the spacers such that a first top surface of the high-k metal gate electrode is substantially diametrically opposite a second bottom surface of the high-k metal gate electrode, and such that a first surface length of the first top surface is not equal to a second surface length of the second bottom surface.

15. The method of claim 14, comprising etching through a photoresist layer before forming the gate dielectric.

16. The method of claim 15, comprising removing a BARC layer after etching through the photoresist layer.

17. The method of claim 16, comprising removing a bottom layer after removing the BARC layer.

18. The method of claim 16, comprising forming the silicon dummy layer such that the top surface length of the top surface is larger than the bottom surface length of the bottom surface.

19. The method of claim 16, comprising forming the high-k metal gate electrode such that the first surface length of the first top surface is larger than the second surface length of the second bottom surface.

20. The method of claim 16, comprising forming an interfacial layer over the substrate before forming the gate dielectric.