SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20150069545A1
• Filed: 01/28/2014
• Published: 03/12/2015
• Est. Priority Date: 09/09/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NOMA, Kenji
• Granted Patent: US 9,190,361 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/167 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H10N 50/01 : Manufacture or treatment
• CPC Class Codes: H10N 50/80 : Constructional details

Abstract

According to one embodiment, a semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer separated from the MRAM chip, surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.

Claims

1. A semiconductor device comprising:

an MRAM chip including a semiconductor substrate and a memory cell array area comprising magnetoresistive elements which are provided on the semiconductor substrate; and

a magnetic shield layer separated from the MRAM chip, surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.

2. The device of claim 1, wherein the magnetic shield layer has a closed loop structure in a first cross section which is perpendicular to a surface of the semiconductor substrate and parallel to the circumferential direction.

3. The device of claim 2, wherein the magnetoresistive elements have magnetizations which are parallel to the first cross section.

4. The device of claim 2, wherein the magnetic shield layer has an end portion in a second cross section which is perpendicular to the first cross section and parallel to the surface of the semiconductor substrate.

5. The device of claim 4, wherein the end portion of the magnetic shield layer is provided outside an end portion of the MRAM chip in the second cross section.

6. The device of claim 1, wherein the magnetic shield layer functions as a package of the MRAM chip.

7. The device of claim 1, further comprising a circuit board on which the MRAM chip is mounted.

8. The device of claim 7, wherein the magnetic shield layer comprises a first magnetic layer between a lower surface of the MRAM chip and the circuit board, and a second magnetic layer covering an upper surface and a side surface of the MRAM chip.

9. The device of claim 8, wherein

the first magnetic layer has an opening in which a conductive line is provided, the conductive line is connected to an external terminal of the MRAM chip;

and

the opening is provided outside an end portion of the MRAM chip in a direction which is parallel to a surface of the semiconductor substrate.

10. The device of claim 8, further comprising a resin covering the upper surface and the side surface of the MRAM chip,

wherein the second magnetic layer is provided on the resin.

11. The device of claim 7, further comprising a package on the circuit board, the package covering the upper surface and the side surface of the MRAM chip,

wherein the magnetic shield layer contacts the package.

12. The device of claim 7, wherein

the circuit board comprises wiring layers;

and

the magnetic shield layer is provided in one of the wiring layers.

13. A method of manufacturing a semiconductor device, the method comprising:

forming a MRAM chip including a semiconductor substrate and a memory cell array area comprising magnetoresistive elements which are provided on the semiconductor substrate;

mounting the MRAM chip on a first magnetic layer of a circuit board;

forming a second magnetic layer on the circuit board, the second magnetic layer covering an upper surface and a side surface of the MRAM chip; and

forming a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip and having a closed magnetic path by the first and second magnetic layers.

14. The method of claim 13, wherein the magnetic shield layer has a closed loop structure in a first cross section which is perpendicular to a surface of the semiconductor substrate and parallel to the circumferential direction.

15. The method of claim 14, wherein the magnetoresistive elements have magnetizations which are parallel to the first cross section.

16. The method of claim 14, wherein the magnetic shield layer has an end portion in a second cross section which is perpendicular to the first cross section and parallel to the surface of the semiconductor substrate.

17. The method of claim 16, wherein the end portion of the magnetic shield layer is provided outside an end portion of the MRAM chip in the second cross section.

18. The method of claim 13, wherein the magnetic shield layer functions as a package of the MRAM chip.

19. The method of claim 13, further comprising forming a resin layer covering the upper surface and the side surface of the MRAM chip.

20. The method of claim 19, wherein the second magnetic layer is formed on the resin layer.