MAGNETIC MEMORY DEVICE

• US 20150069546A1
• Filed: 02/11/2014
• Published: 03/12/2015
• Est. Priority Date: 09/09/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KOBAYASHI, Shinya, NOMA, Kenji, OYAMATSU, Hisato
• Granted Patent: US 9,041,130 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

According to one embodiment, a magnetic memory device includes a semiconductor substrate, a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween, a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements, and a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area.

Claims

1. A magnetic memory device comprising:

a semiconductor substrate;

a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween;

a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements; and

a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area.

2. The device of claim 1, wherein the closed magnetic path area functions as a package of the memory cell array area and the magnetic field generating area.

3. The device of claim 1, wherein the magnetic field generating area includes a permanent magnet.

4. The device of claim 1, wherein the magnetic field generating area includes a magnetic layer with an invariable magnetization.

5. The device of claim 1, wherein

the reference layer and the storage layer has a perpendicular magnetization which is perpendicular to a surface of the semiconductor substrate, and

the first magnetic field has magnetic lines which are perpendicular to the surface of the semiconductor substrate in the memory cell array area.

6. The device of claim 1, wherein

the reference layer and the storage layer has a in-plane magnetization which is parallel to a surface of the semiconductor substrate, and

the first magnetic field has magnetic lines which are parallel to the surface of the semiconductor substrate in the memory cell array area.

7. The device of claim 1, further comprising:

a memory chip including the semiconductor substrate, the memory cell array area, and the magnetic field generating area.

8. The device of claim 7, wherein the magnetic field generating area is a magnetic layer stacked on the memory cell array area and shared by the magnetoresistive elements.

9. The device of claim 8, wherein

the memory chip includes a peripheral circuit area, and

the magnetic layer is provided in the memory cell array area and not provided in the peripheral circuit area.

10. The device of claim 9, wherein the peripheral circuit area includes an external terminal connected to an external element which is provided out of the memory chip.

11. The device of claim 8, further comprising:

a bit line connected to the magnetoresistive elements, the magnetic layer stacked on the bit line and extending in a direction in which the bit line extends.

12. The device of claim 8, further comprising:

a bit line connected to the magnetoresistive elements, the bit line stacked on the magnetic layer extending in a direction in which the bit line extends.

13. The device of claim 1, further comprising:

a memory chip including the semiconductor substrate and the memory cell array area,

wherein the magnetic field generating area is provided out of the memory chip.

14. The device of claim 13, wherein the magnetic field generating area is a magnetic layer provided on the memory chip and shared by the magnetoresistive elements.

15. The device of claim 14, wherein the magnetic layer includes a permanent magnet.

16. The device of claim 13, wherein the magnetic field generating area is a magnetic layer provided under the memory chip and shared by the magnetoresistive elements.

17. The device of claim 16, wherein the magnetic layer includes a permanent magnet.

18. The device of claim 1, further comprising:

a memory chip including the semiconductor substrate and the memory cell array area; and

a circuit board on which the memory chip is mounted,

wherein the magnetic field generating area is provided in the circuit board.

19. The device of claim 18, wherein

the circuit board comprises wiring layers, and

the magnetic field generating area is a magnetic layer provided in one of the wiring layers and shared by the magnetoresistive elements.

20. The device of claim 19, wherein the magnetic layer has an invariable magnetization.