Multilayer High Voltage Isolation Barrier in an Integrated Circuit

• US 20150069572A1
• Filed: 09/12/2013
• Published: 03/12/2015
• Est. Priority Date: 09/12/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Khanolkar, Vijaylaxmi, Poddar, Anindya, Frattini, Giovanni, Massolini, Roberto Giampiero, Walberg, Randall
• Granted Patent: US 9,035,422 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 2027/2819 Planar transformers with printed windings, e.g. surrounded by two cores and to be mounted on printed circuit
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/19107 off-chip wires

Abstract

A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil formed in one or more dielectric laminate layers of the substrate, a second inductor coil formed in one or more dielectric laminate layers of the substrate, and an isolation barrier comprising two or more dielectric laminate layers of the multilayer substrate positioned between the first inductor coil and the second inductor coil. The transformer may be mounted on a lead frame along with one or more integrated circuits and molded into a packaged isolation device.

Claims

1. A semiconductor package comprising:

a transformer formed within a multilayer dielectric laminate substrate, wherein the transformer comprises;

a first inductor coil formed in one or more dielectric laminate layers of the substrate;

a second inductor coil formed in one or more dielectric laminate layers of the multilayer substrate; and

an isolation barrier comprising two or more dielectric laminate layers of the substrate positioned between the first inductor coil and the second inductor coil.

2. The transformer of claim 1, wherein the two or more dielectric layers of the isolation barrier comprise Bismaleimide Triazine (BT).

3. The transformer of claim 1, further comprising:

a first set of terminals formed in a top dielectric laminate layer of the substrate coupled to the first inductor coil; and

a second set of terminals formed in the top dielectric laminate of the substrate coupled to the second inductor coil by a set of vias, wherein each via of the set of vias comprise blind or buried vias, whereby voltage breakdown is maximized.

4. The transformer of claim 1, wherein the first inductor coil has a thickness greater than 12 um.

5. The semiconductor package of claim 3, further comprising:

a leadframe having a split die attachment pad (DAP) configured to support the transformer; and

a first integrated circuit (IC) mounted on a portion of the split DAP.

6. The semiconductor package of claim 5, further comprising a second integrated circuit mounted on a separate portion of the split DAP.

7. The semiconductor package of claim 5, further comprising mold compound that encapsulates the transformer and the first IC.

8. The semiconductor package of claim 3, wherein the leadframe is constrained to not have any metal in proximity to the first inductor coil or to the second inductor coil.

9. A semiconductor package comprising:

a leadframe having a split die attachment pad (DAP);

a first integrated circuit (IC) mounted on a first portion of the split DAP; and

an isolation transformer mounted to span the split DAP, wherein the transformer comprises a multilayer dielectric laminate substrate, wherein the transformer has a multilayer laminate isolation barrier.

10. The semiconductor package of claim 9, further comprising a second integrated circuit mounted on a separate portion of the split DAP.

11. The semiconductor package of claim 9, further comprising mold compound that encapsulates the transformer and the first IC.

12. The semiconductor package of claim 9, wherein the transformer comprises:

a first inductor coil formed in one or more dielectric laminate layers of the substrate;

a second inductor coil formed in one or more dielectric laminate layers of the multilayer substrate; and

wherein the isolation barrier comprises two or more dielectric laminate layers of the substrate positioned between the first inductor coil and the second inductor coil.

13. The semiconductor package of claim 12, wherein the leadframe is constrained to not have any metal in proximity to the first inductor coil or to the second inductor coil.