SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• US 20150070050A1
• Filed: 02/26/2014
• Published: 03/12/2015
• Est. Priority Date: 09/06/2013
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SUZUKI, Azuma, HARA, Hiroyuki
• Granted Patent: US 8,994,405 B1
• Time in Patent Office: Days
• US Class Current: 326/98
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages.

Claims

1. A semiconductor integrated circuit device comprising:

a first flip-flop circuit configured to receive data in synchronization with a first clock signal;

a logic circuit configured to perform a predetermined process on data output from the first flip-flop circuit;

a hold buffer circuit configured to delay transmission of an output of the logic circuit;

a second flip-flop circuit configured to receive an output of the hold buffer circuit in synchronization with a second clock signal; and

a power supply circuit configured to select a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage,

wherein a power supply voltage supplied to the hold buffer circuit remains the same even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between the first and second power supply voltages.

2. The semiconductor integrated circuit device according to claim 1, wherein

the first flip-flop circuit, the second flip-flop circuit, the logic circuit, and the hold buffer circuit are designed under a condition in which the first power supply voltage is applied, and the power supply voltage supplied to the hold buffer circuit remains at the first power supply voltage even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes from the first power supply voltage to the second power supply voltage.

3. The semiconductor integrated circuit device according to claim 1, wherein

the first flip-flop circuit, the second flip-flop circuit, the logic circuit, and the hold buffer circuit are designed under a condition in which the second power supply voltage is applied, and the power supply voltage supplied to the hold buffer circuit remains at the second power supply voltage even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes from the second power supply voltage to the first power supply voltage.

4. The semiconductor integrated circuit device according to claim 1, further comprising:

a first power supply line that connects an output of the power supply circuit to power supply inputs of the first flip-flop circuit, the logic circuit, and the second flip-flop circuit, and

a second power supply line that supplies one of the first and second power supply voltages to an input of the hold buffer circuit.

5. The semiconductor integrated circuit device according to claim 4, wherein

the hold buffer circuit includes inverter circuits of an even number of stages connected in series.

6. The semiconductor integrated circuit device according to claim 4, further comprising:

a clock signal supply line connected to a clock input of the first flip-flop circuit to supply the first clock signal and to a clock input of the second flip-flop circuit to supply the second clock signal.

7. The semiconductor integrated circuit device according to claim 1, further comprising:

a high voltage power supply line connected to a first power supply input of the power supply circuit;

a low voltage power supply line connected to a second power supply input of the power supply circuit;

a variable voltage power supply line connected between an output of the power supply circuit and power supply inputs of the first flip-flop circuit, the logic circuit, and the second flip-flop circuit; and

a bypass power supply line connected between one of the high and low voltage power supply lines and a power supply input of the hold buffer circuit.

8. A semiconductor integrated circuit device comprising:

a first flip-flop circuit configured to receive data in synchronization with a first clock signal;

a logic circuit configured to perform a predetermined process on data output from the first flip-flop circuit;

a hold buffer circuit configured to delay transmission of an output of the logic circuit;

a second flip-flop circuit configured to receive an output of the hold buffer circuit in synchronization with a second clock signal;

a power supply circuit configured to select a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage;

a first power supply line that connects an output of the power supply circuit to power supply inputs of the first flip-flop circuit, the logic circuit, and the second flip-flop circuit; and

a second power supply line that supplies one of the first and second power supply voltages to an input of the hold buffer circuit.

9. The semiconductor integrated circuit device according to claim 8, wherein

the first flip-flop circuit, the second flip-flop circuit, the logic circuit, and the hold buffer circuit are designed under a condition in which the first power supply voltage is applied, and the power supply voltage supplied to the hold buffer circuit remains at the first power supply voltage even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes from the first power supply voltage to the second power supply voltage.

10. The semiconductor integrated circuit device according to claim 8, wherein

the first flip-flop circuit, the second flip-flop circuit, the logic circuit, and the hold buffer circuit are designed under a condition in which the second power supply voltage is applied, and the power supply voltage supplied to the hold buffer circuit remains at the second power supply voltage even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes from the second power supply voltage to the first power supply voltage.

11. The semiconductor integrated circuit device according to claim 8, wherein

the hold buffer circuit includes inverter circuits of an even number of stages connected in series.

12. The semiconductor integrated circuit device according to claim 8, further comprising:

a clock signal supply line connected to a clock input of the first flip-flop circuit to supply the first clock signal and to a clock input of the second flip-flop circuit to supply the second clock signal.

13. The semiconductor integrated circuit device according to claim 8, further comprising:

a high voltage power supply line connected to a first power supply input of the power supply circuit; and

a low voltage power supply line connected to a second power supply input of the power supply circuit,

wherein the one of the high and low voltage power supply lines is directly connected to the second power supply line.

14. A method of processing data through serially connected circuit elements of a semiconductor integrated circuit device that include a first flip-flop circuit, a logic circuit, a hold buffer circuit, and a second flip-flop circuit, said method comprising:

receiving data in the first flip-flop circuit in synchronization with a first clock signal;

performing a predetermined process on data output from the first flip-flop circuit with the logic circuit;

delaying transmission of an output of the logic circuit with the hold buffer circuit;

receiving an output of the hold buffer circuit in a second flip-flop circuit in synchronization with the second clock signal; and

selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage,

wherein a power supply voltage supplied to the hold buffer circuit remains the same even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between the first and second power supply voltages.

15. The method according to claim 14, wherein

the first flip-flop circuit, the second flip-flop circuit, the logic circuit, and the hold buffer circuit are designed under a condition in which the first power supply voltage is applied, and the power supply voltage supplied to the hold buffer circuit remains at the first power supply voltage even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes from the first power supply voltage to the second power supply voltage.

16. The method according to claim 14, wherein

the first flip-flop circuit, the second flip-flop circuit, the logic circuit, and the hold buffer circuit are designed under a condition in which the second power supply voltage is applied, and the power supply voltage supplied to the hold buffer circuit remains at the second power supply voltage even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes from the second power supply voltage to the first power supply voltage.

17. The method according to claim 14, wherein the semiconductor integrated circuit device further includes:

a first power supply line that connects an output of the power supply circuit to power supply inputs of the first flip-flop circuit, the logic circuit, and the second flip-flop circuit, and

a second power supply line that supplies one of the first and second power supply voltages to an input of the hold buffer circuit.

18. The method according to claim 17, wherein

the hold buffer circuit includes inverter circuits of an even number of stages connected in series.

19. The method according to claim 14, wherein the semiconductor integrated circuit device further includes:

a clock signal supply line connected to a clock input of the first flip-flop circuit to supply the first clock signal and to a clock input of the second flip-flop circuit to supply the second clock signal.

20. The method according to claim 14, wherein the semiconductor integrated circuit device further includes:

a high voltage power supply line connected to a first power supply input of the power supply circuit;

a low voltage power supply line connected to a second power supply input of the power supply circuit;

a variable voltage power supply line connected between an output of the power supply circuit and power supply inputs of the first flip-flop circuit, the logic circuit, and the second flip-flop circuit; and

a bypass power supply line connected between one of the high and low voltage power supply lines and a power supply input of the hold buffer circuit.