NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20150071005A1
• Filed: 02/27/2014
• Published: 03/12/2015
• Est. Priority Date: 09/11/2013
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MAEJIMA, Hiroshi, KAMATA, Yoshihiko
• Application Number:
  US14/192,380
• Publication Number:
  US 20150071005A1
• Time in Patent Office: Days
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A NAND type flash memory includes a plurality of memory cells, a bit line electrically connected to a first end of the memory cells, a source line electrically connected to a second end of the memory cells, and a control unit configured to carry out one of first and second sense operations, the first sense operation being carried out when a first read command is received and the second sense operation being carried out when a second read command is received, the first read command being different from the second read command.

Claims

1. A nonvolatile semiconductor memory device comprising:

a plurality of memory cells;

a bit line electrically connected to a first end of the memory cells;

a source line electrically connected to a second end of the memory cells; and

a control unit configured to carry out one of first and second sense operations, the first sense operation being carried out when a first read command is received and the second sense operation being carried out when a second read command is received, the first read command being different from the second read command.

2. The device according to claim 1, wherein the source line is electrically connected to ground when the first sense operation is carried out.

3. The device according to claim 2, wherein the source line is electrically connected to a reference voltage source when the second sense operation is carried out.

4. The device according to claim 1, wherein one of the first and second sense operations is carried out during a read operation.

5. The device according to claim 1, wherein one of the first and second sense operations is carried out during a write operation.

6. The device according to claim 1, further comprising:

a plurality of bit lines electrically connected to the memory cells, wherein all of the bit lines are sensed collectively when the first sense operation is carried out.

7. The device according to claim 1, further comprising:

a plurality of bit lines electrically connected to the memory cells, wherein a first group of the bit lines are sensed collectively and then a second group of the bit lines are sensed collectively, when the first sense operation is carried out.

8. The device according to claim 7, wherein the bit lines in the first group are different from the bit lines in the second group.

9. The device according to claim 1, wherein

the plurality of memory cells are stacked above a semiconductor substrate, and

a current path of the plurality of memory cells connected in series is disposed in a first direction perpendicular to the semiconductor substrate.

10. The device according to claim 1, wherein

the plurality of memory cells are stacked above a semiconductor substrate, and

a current path of the plurality of memory cells connected in series is disposed in a second direction parallel to the semiconductor substrate.

11. A nonvolatile semiconductor memory device comprising:

a plurality of memory cells;

a bit line electrically connected to a first end of the memory cells;

a source line electrically connected to a second end of the memory cells; and

a control unit configured to select one of a first sense operation during which the source line is electrically connected to ground and a second sense operation during which the source line is electrically connected to a reference voltage source, according to a type of command received by the memory device.

12. The device according to claim 11, wherein the command is a read command.

13. The device according to claim 11, wherein the command is a write command.

14. The device according to claim 11, further comprising:

a plurality of bit lines electrically connected to the memory cells, wherein all of the bit lines are sensed collectively when the first sense operation is carried out.

15. The device according to claim 11, further comprising:

a plurality of bit lines electrically connected to the memory cells, wherein a first group of the bit lines are sensed collectively and then a second group of the bit lines are sensed collectively, when the first sense operation is carried out.

16. The device according to claim 15, wherein the bit lines in the first group are different from the bit lines in the second group.

17. The device according to claim 11, wherein

the plurality of memory cells are stacked above a semiconductor substrate, and

a current path of the plurality of memory cells connected in series is disposed in a first direction perpendicular to the semiconductor substrate.

18. The device according to claim 11, wherein

the plurality of memory cells are stacked above a semiconductor substrate, and

a current path of the plurality of memory cells connected in series is disposed in a second direction parallel to the semiconductor substrate.

19. A method of performing a sensing operation in a nonvolatile semiconductor memory device including a plurality of memory cells, a bit line electrically connected to a first end of the memory cells, and a source line electrically connected to a second end of the memory cells, said method comprising:

receiving a command; and

selecting one of a first sense operation during which the source line is electrically connected to ground and a second sense operation during which the source line is electrically connected to a reference voltage source, according to a type of the received command.

20. The method of claim 19, wherein the first sense operation is selected in response to a fast read command and the second sense operation is selected in response to a normal read command.