METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE

• US 20150074305A1
• Filed: 09/08/2014
• Published: 03/12/2015
• Est. Priority Date: 09/09/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro, Wietfeldt, Richard Dominic, Wiley, George Alan
• Granted Patent: US 9,519,603 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/378 using a parallel poll method
• CPC Class Codes: G06F 2213/3602 Coding information on a single line

Abstract

To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Claims

1. A device, comprising:

a single line interrupt request (IRQ) bus to which a plurality of master devices are coupled, wherein the plurality of master devices include an active master device and one or more inactive master devices;

a data bus to which the plurality of master devices are also coupled;

a processing circuit within the active master device, the processing circuit adapted to;

manage communications over the data bus for all devices coupled to the data bus based on interrupt signals asserted over the IRQ bus;

monitor the IRQ bus to ascertain when an IRQ signal has been asserted;

poll the inactive master devices over the data bus to ascertain which inactive master device asserted the IRQ signal on the IRQ bus; and

hand over control of the data bus to an asserting inactive master device upon obtaining an indication from the inactive master device that it made a master request.

2. The device of claim 1, wherein the master request from the inactive master device is obtained over the IRQ bus.

3. The device of claim 1, wherein the indication from the inactive master device is obtained over the data bus.

4. The device of claim 1, wherein the processing circuit is further adapted to:

send an indicator to the asserting inactive master device to transfer control of the data bus.

5. The device of claim 1, wherein the processing circuit is further adapted to:

identify the asserting inactive master device with which the IRQ signal is associated based on the obtained indicator.

6. The device of claim 1, wherein the processing circuit is further adapted to:

identify a group of devices with which the IRQ signal is associated.

7. The device of claim 6, wherein the processing circuit is further adapted to:

scan the devices for the identified group to ascertain which device asserted the IRQ signal on the IRQ bus.

8. The device of claim 6, wherein the IRQ signal associated with each group has a different pulse width than other IRQ signals associated with other groups.

9. The device of claim 6, wherein each group of devices includes a single device.

10. The device of claim 1, wherein the processing circuit is further adapted to:

ascertain if a polled inactive master device asserted the IRQ signal and made the master request by looking at a particular bit in a status register obtained from each of the polled inactive master devices.

11. The device of claim 1, wherein the indication from the inactive master device that it made a master request is encoded within an unused bit obtained by coding the transmissions from the one or more inactive master devices to the active master device.

12. The device of claim 1, wherein at least the asserting inactive master device switches between a master mode of operation and a slave mode of operation.

13. A method operational on a device, comprising:

managing communications over a data bus for all devices coupled to the data bus based on interrupt signals asserted over a single line interrupt request (IRQ) bus, wherein a plurality of master devices are coupled to IRQ bus and the data bus;

monitoring the IRQ bus to ascertain when an IRQ signal has been asserted;

polling the inactive master devices over the data bus to ascertain which inactive master device asserted the IRQ signal on the IRQ bus; and

handing over control of the data bus to an asserting inactive master device upon obtaining an indication from the inactive master device that it made a master request.

14. The method of claim 13, further comprising:

sending an indicator to the asserting inactive master device to transfer control of the data bus.

15. The method of claim 13, further comprising:

identifying the asserting inactive master device with which the IRQ signal is associated based on the obtained indicator.

16. The method of claim 13, further comprising:

identifying a group of devices with which the IRQ signal is associated.

17. The method of claim 16, further comprising:

scanning the devices for the identified group to ascertain which device asserted the IRQ signal on the IRQ bus.

18. The method of claim 16, wherein the IRQ signal associated with each group has a different pulse width than other IRQ signals associated with other groups.

19. The method of claim 13, further comprising:

ascertaining if a polled inactive master device asserted the IRQ signal and made the master request by looking at a particular bit in a status register obtained from each of the polled inactive master devices.

20. The method of claim 13, wherein the data bus that is a camera control interface extension (CCIe)-compatible bus.

21. A non-transitory machine-readable storage medium having one or more instructions stored thereon, which when executed by at least one processor causes the at least one processor to:

manage communications over a data bus for all devices coupled to the data bus based on interrupt signals asserted over an interrupt request (IRQ) bus, wherein a plurality of master devices are coupled to IRQ bus and the data bus;

monitor the IRQ bus to ascertain when an IRQ signal has been asserted;

poll the inactive master devices over the data bus to ascertain which inactive master device asserted the IRQ signal on the IRQ bus; and

hand over control of the data bus to an asserting inactive master device upon obtaining an indication from the inactive master device that it made a master request.

22. A device, comprising:

a first interface to couple to a single line interrupt request (IRQ) bus to which a plurality of other devices are coupled;

a second interface to couple to a data bus to which the plurality of other devices are also coupled;

a processing circuit coupled to the first interface and second interface, the processing circuit adapted to;

manage communications over the data bus for all devices coupled to the data bus based on interrupt signals asserted over the IRQ bus;

monitor the IRQ bus to ascertain when an IRQ signal has been asserted;

poll the inactive master devices over the data bus to ascertain which inactive master device asserted the IRQ signal on the IRQ bus; and

hand over control of the data bus to an asserting inactive master device upon obtaining an indication from the inactive master device that it made a master request.

23. The device of claim 22, wherein the master request from the inactive master device is obtained over the first interface.

24. The device of claim 22, wherein the indication from the inactive master device is obtained over the second interface.

25. The device of claim 22, wherein the data bus is a camera control interface extension (CCIe)-compatible bus.

26. The device of claim 22, wherein the data bus is a bidirectional bus.

27. The device of claim 22, wherein the processing circuit is further adapted to:

send an indicator to the asserting inactive master device over the data bus to transfer control of the data bus.

28. The device of claim 22, wherein the processing circuit is further adapted to:

ascertain if a polled inactive master device asserted the IRQ signal and made the master request by looking at a particular bit in a status register obtained from each of the polled inactive master devices.