HYBRID MAIN MEMORY USING A FINE-GRAIN LEVEL OF REMAPPING

• US 20150074339A1
• Filed: 09/08/2014
• Published: 03/12/2015
• Est. Priority Date: 09/10/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Hicamp Systems Incorporated
• Inventors: Cheriton, David R.
• Granted Patent: US 9,898,410 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory address to a first line in the first portion. Said mapping provides an indication that the first line is not immediately accessible in the first portion.

Claims

1. A hybrid memory system comprising:

a hybrid memory comprising a first portion; and

a hardware memory controller coupled with the hybrid memory and configured to;

access the hybrid memory using a translation line, wherein the translation line maps a first physical address to a first line in the first portion,

wherein the said mapping provides an indication that the first line is not immediately accessible in the first portion.

2. A system as recited in claim 1, wherein the hybrid memory further comprises a second portion, wherein the first portion has different characteristics compared to the second portion.

3. A system as recited in claim 2, wherein the first portion comprises volatile memory and the second portion comprises non-volatile memory.

4. A system as recited in claim 2, wherein to remap includes transferring line contents associated with the second portion to the first portion.

5. A system as recited in claim 2, wherein the hardware memory controller is further configured to detect access to the second portion, prior to providing an indication.

6. A system as recited in claim 2, wherein a second line associated with the second portion is unmapped such than other intervention occurs when an associated processor attempts to access it.

7. A system as recited in claim 1, wherein the hardware memory controller is further configured to, based at least in part on the indication, modify the translation line, wherein the modified translation line maps the physical address to a first data line in the first portion that is readily accessible.

8. A system as recited in claim 7, wherein a separate data structure is used to determine the modification of the translation line.

9. A system as recited in claim 1, wherein the hardware memory controller is further configured to receive a remapping of the translation line from an auxiliary module.

10. A system as recited in claim 1, wherein the hardware memory controller is further configured to prefetch other data lines.

11. A system as recited in claim 1, wherein the hardware memory controller is further configured to remap lines associated with a virtual memory page.

12. A system as recited in claim 11, wherein remapping the virtual memory page permits an associated processor to continue after the translation line maps the first physical address to the first line in the first portion.

13. A system as recited in claim 11, wherein virtual address mapping is handled in software.

14. A system as recited in claim 1, wherein the hardware memory controller is further to configured to provide transactional update support.

15. A system as recited in claim 1, wherein the hardware memory controller is further configured to support writing modified lines of memory to a log area in the second portion.

16. A system as recited in claim 15, wherein writeback is recorded in the log area.

17. A system as recited in claim 1, wherein the hardware memory controller is further configured to maintain an undo log area and a redo log area.

18. A method, comprising

accessing a hybrid memory using a translation line, wherein

the hybrid memory comprises a first portion;

and

the translation line maps a first physical memory address to a first line in the first portion,

wherein the said mapping provides an indication that the first line is not immediately accessible in the first portion.

19. A method of supporting a hybrid main memory in hardware, comprising:

using a memory controller to remap at least in part by translating a plurality of physical memory addresses, each associated with a plurality of current content locations;

associating the memory controller with a hybrid main memory, wherein the hybrid main memory comprises a primary memory technology area and an alternative memory technology area;

associating the memory controller with a processor; and

on read of a physical address associated with an alternative data line that is currently stored in the alternative memory technology area, transferring the alternative data line to the processor and updating the mapping state to associate the physical address with the primary memory area.

20. A method as recited in claim 19, wherein the unit of transfer is a memory line.

21. A method as recited in claim 19, wherein one or more translation lines are used at least in part for remapping, each potentially remapping multiple data lines.

22. A method as recited in claim 19, wherein another translation line is updated to indicate availability of associated data lines in the primary memory technology area.

23. A method as recited in claim 19, wherein additional data lines referenced by another translation line are prefetched into the primary memory technology area after a reference to the alternative data line.

24. A method as recited in claim 19, further comprising providing line sharing between translation lines.

25. A method as recited in claim 19, further comprising providing line granularity deduplication.

26. A method as recited in claim 19, further comprising providing transactional update support.

27. A method as recited in claim 19, further comprising, on write back of a data line from the processor, performing the write according to the remapping.