MEMORY CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM

• US 20150074346A1
• Filed: 07/06/2014
• Published: 03/12/2015
• Est. Priority Date: 09/06/2013
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Luo, Yan-Bin, Chang, Sheng-Ming, Liou, Ming-Shi, Hung, Chih-Chien, Hsieh, Bo-Wei, Chen, Shang-Pin
• Granted Patent: US 10,083,728 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

Claims

1. A memory controller, comprising:

a chip-select transmitter, arranged to generate a first signal for selecting one memory device from a plurality of memory devices and generate a second signal which is an inversed version of the first signal;

a first pin, arranged to output the first signal; and

a second pin, arranged to output the second signal;

wherein the first signal and the second signal are configured to be a differential signal.

2. The memory controller of claim 1, wherein the chip-select transmitter generates the first signal and the second signal synchronously.

3. The memory controller of claim 1, wherein when a notification is acquired to be performed by the first signal and the second signal, the first signal is asserted to a first voltage level for a specific time interval, and the second signal is asserted to a second voltage level different from the first voltage level for the specific time interval.

4. The memory controller of claim 3, wherein the memory controller further provides a clock output, and the specific time interval equals to a period of the clock output.

5. The memory controller of claim 1, wherein the memory controller is a DDR3 memory controller for controlling a DDR3 memory module.

6. A memory module, comprising:

a first pin, arranged to receive a first signal;

a second pin, arranged to receive a second signal;

a first conducting path, having a first end coupled to the first pin;

at least one memory chip, coupled to the first conducting path for receiving the first signal;

a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and

a second conducting path, having a first end coupled to second pin for conducting the second signal to a second terminal of the predetermined resistor;

wherein the first signal and the second signal are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

7. The memory module of claim 6, wherein the first signal and the second signal reach the predetermined resistor substantially at the same time via the first conducting path and the second conducting path respectively.

8. The memory module of claim 6, wherein a first impedance obtained by looking into the second end of the first conducting path substantially equals a second impedance obtained by looking into the first terminal of the predetermined resistor.

9. The memory module of claim 6, wherein when a pair of signals is sent to the at least one memory chip via the first signal and the second signal for enabling a memory chip of the at least one memory chip, the first signal is asserted to a first voltage level for a specific time interval, and the second signal is asserted to a second voltage level different from the first voltage level for the specific time interval.

10. The memory module of claim 9, wherein the memory controller further receives a clock input, and the specific time interval equals to a period of the clock output.

11. The memory module of claim 6, wherein the memory module is a DDR3 memory module.

12. The memory module of claim 6, wherein the predetermined resistor is a 100 Ohm resistor.

13. A memory system, comprising:

a memory controller; and

a memory module, comprising at least one memory chip;

wherein memory controller generates a differential pair of a first signal and a second signal to the memory module, and the first signal and the second signal are synchronous with each other for enabling a selected memory chip from the at least one memory chip to be accessed by the memory controller.

14. The memory system of claim 13, wherein when a notification is acquired to be performed by the first signal and the second signal, the first signal is asserted to a first voltage level for a specific time interval, and the second signal is asserted to a second voltage level different from the first voltage level for the specific time interval.

15. The memory system of claim 14, wherein the memory controller further provides a clock output to the memory module, and the specific time interval equals to a period of the clock output.

16. The memory system of claim 13, wherein the memory module receives the first signal and the second signal by a first pin and a second pin respectively;

and a first impedance obtained by looking into the second pin substantially equals a second impedance obtained by looking into the first pin.

17. The memory system of claim 13, wherein the memory controller is a DDR3 memory controller, and the memory module is a DDR3 memory module.

18. The memory system of claim 13, wherein the first signal and the second signal collide at a predetermined resistor of the memory module.

19. The memory module of claim 18, wherein the predetermined resistor is a 100 Ohm resistor.