MEMORY CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM
First Claim
1. A memory controller, comprising:
- a chip-select transmitter, arranged to generate a first signal for selecting one memory device from a plurality of memory devices and generate a second signal which is an inversed version of the first signal;
a first pin, arranged to output the first signal; and
a second pin, arranged to output the second signal;
wherein the first signal and the second signal are configured to be a differential signal.
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Accused Products
Abstract
A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.
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Citations
19 Claims
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1. A memory controller, comprising:
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a chip-select transmitter, arranged to generate a first signal for selecting one memory device from a plurality of memory devices and generate a second signal which is an inversed version of the first signal; a first pin, arranged to output the first signal; and a second pin, arranged to output the second signal; wherein the first signal and the second signal are configured to be a differential signal. - View Dependent Claims (2, 3, 4, 5)
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6. A memory module, comprising:
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a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second signal to a second terminal of the predetermined resistor; wherein the first signal and the second signal are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A memory system, comprising:
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a memory controller; and a memory module, comprising at least one memory chip; wherein memory controller generates a differential pair of a first signal and a second signal to the memory module, and the first signal and the second signal are synchronous with each other for enabling a selected memory chip from the at least one memory chip to be accessed by the memory controller. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification