HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION

• US 20150076584A1
• Filed: 03/25/2014
• Published: 03/19/2015
• Est. Priority Date: 09/17/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Raghuveer S. Makala
• Inventors: Pachamuthu, Jayavel, Alsmeier, Johann, Makala, Raghuveer S., Lee, Yao-Sheng
• Granted Patent: US 9,460,931 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.

Claims

1. A method of fabricating a memory device, comprising:

forming a protrusion comprising a semiconductor material over a major surface of a semiconductor substrate, the protrusion having a top surface substantially parallel to the major surface of the substrate;

forming an etch stop layer over the top surface of the protrusion;

forming a stack of alternating layers of a first material and a second material different from the first material over the etch stop layer;

etching the stack through a mask to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer;

etching the etch stop layer to provide a void area between the top surface of the protrusion and a bottom of the memory opening, the void area having a second width dimension that is larger than the first width dimension;

forming at least a portion of a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion;

etching the memory film to expose the top surface of the protrusion; and

forming a semiconductor channel in the memory opening such that the semiconductor channel is electrically coupled to the protrusion and the at least a portion of the memory film is located between the semiconductor channel and the sidewall of the memory opening.

2. The method of claim 1, wherein the stack is etched to the etch stop layer using a first etching process and the etch stop layer is etched to provide the void area using a second etching process different than the first etching process, and the etch stop layer comprises a material with a higher etch rate using the second etching process than with the first etching process.

3. The method of claim 2, wherein the etch stop layer comprises a material with a higher etch rate than the stack and the protrusion using the second etching process.

4. The method of claim 2, wherein the first etching process comprises a reactive ion etching process and the second etching process comprises a wet etching process.

5. The method of claim 1, wherein the etch stop layer comprises intrinsic polysilicon.

6. The method of claim 1, wherein the etch stop layer comprises at least one of a nitride and an oxide material.

7. The method of claim 1, wherein the memory film comprises blocking dielectric, a charge trapping layer or floating gate and a tunnel dielectric, and the tunnel dielectric is located between the charge trapping layer or floating gate and the semiconductor channel.

8. The method of claim 7, wherein the memory device comprises a three dimensional monolithic NAND string and wherein the second material layers comprise control gate electrodes or sacrificial layers which are replaced with conductive control gate electrodes after forming the semiconductor channel.

9. The method of claim 1, further comprising:

forming a sacrificial semiconductor layer over the at least a portion of the memory film along the sidewall of the memory opening and in the void area over the top surface of the protrusion;

etching the sacrificial semiconductor layer and the memory film to expose the top surface of the protrusion, wherein the semiconductor channel is formed over the sacrificial semiconductor layer along at least the sidewall of the memory opening.

10. The method of claim 9, wherein the sacrificial semiconductor layer comprises intrinsic polysilicon.

11. The method of claim 1, wherein etching the memory film to expose the top surface of the protrusion comprises forming a generally cylindrically-shaped opening through the memory film in the void area to expose the top surface of the protrusion, and forming the semiconductor channel comprises forming a generally cylindrically-shaped protruding region of the semiconductor channel within the generally cylindrically-shaped opening such that a bottom surface of the protruding region contacts the top surface of the protrusion.

12. The method of claim 1, wherein:

the protrusion comprises a rail or pillar shaped channel of a select gate transistor having a first side surface and a second side surface opposite the first side surface;

a select gate electrode extends generally parallel to the major surface of the substrate and adjacent to the first and second side surfaces of the protrusion; and

a gate insulating layer is located between the select gate electrode and the first and second side surfaces of the protrusion.

13. The method of claim 12, wherein the protrusion comprises epitaxially-grown silicon and at least one additional material layer over the epitaxially-grown silicon, wherein the at least one additional material layer comprises at least one of an additional semiconductor material, a metal and a metal nitride.

14. The method of claim 13, wherein the at least one additional material layer comprises polysilicon that is formed over the epitaxially-grown silicon using plasma enhanced chemical vapor deposition.

15. The method of claim 13, wherein the at least one additional material layer comprises at least one of a metal and a metal nitride, the method further comprising selectively annealing the memory device to form a metal silicide in an interface region between the semiconductor channel and the protrusion.

16. The method of claim 15, wherein the selective annealing is performed using a laser.

17. The method of claim 16, wherein the metal silicide comprises at least one of WSi₂, TaSi₂, TiSiN, TiSi₂ and CoSi₂.

18. A memory device, comprising:

a semiconductor substrate having a major surface;

a protrusion comprising a semiconductor material over the major surface of the semiconductor substrate, the protrusion having a top surface substantially parallel to the major surface of the substrate, a first side surface and a second side surface opposite the first side surface;

a select gate electrode extending over and parallel to the major surface of the semiconductor substrate and adjacent to the first and second side surfaces of the protrusion;

a gate insulating layer extending between the select gate electrode and the major surface of the substrate and between the select gate electrode and the first and second side surfaces of the protrusion;

a stack of alternating insulating material layers and control gate electrodes located over the substrate above the protrusion and the select gate electrode and having a memory opening extending through the layer stack in a direction substantially perpendicular to the major surface of the substrate;

a semiconductor channel having at least one first portion extending substantially perpendicular to the major surface of the substrate in the memory opening;

at least one memory film located in the memory opening adjacent to the semiconductor channel, wherein a first portion of the memory film is located between the control gate electrodes and the first portion of the semiconductor channel, and a second portion of the memory film extends over the top surface of the protrusion and defines a generally cylindrically-shaped connector region of the memory opening; and

a generally cylindrically-shaped connector located within the connector region and electrically connecting the protrusion to the semiconductor channel, wherein the memory opening above the connector region is wider than in the connector region.

19. The memory device of claim 18, wherein:

the semiconductor channel further comprises a second portion that comprises a generally cylindrically-shaped region that extends generally parallel to the major surface of the substrate and is located over the second portion of the memory film;

the generally cylindrically-shaped connector extending from the second portion of the semiconductor channel into the connector; and

the second portion of the semiconductor channel has a diameter that is greater than a diameter of the connector.

20. The memory device of claim 19, wherein the first portion of the semiconductor channel defines a generally cylindrically-shaped outer surface extending within the memory opening adjacent to the first portion of the memory film, and the generally cylindrically-shaped region of the second portion of the channel extends radially outward from the generally cylindrically-shaped outer surface defined by the first portion of the semiconductor channel.

21. The memory device of claim 18, further comprising an etch stop layer extending parallel to the major surface of the semiconductor substrate between the select gate electrode and the stack, wherein a portion of the memory opening extending through the etch stop layer is wider than a portion of the memory opening extending through the stack.

22. The memory device of claim 21, wherein the etch stop layer comprises intrinsic polysilicon, silicon oxide or silicon nitride.

23. The memory device of claim 19, wherein the generally cylindrically-shaped connector is a semiconductor connector which comprises a third portion of the semiconductor channel.

24. The memory device of claim 19, wherein semiconductor channel comprises polysilicon and the connector comprises a metal silicide.

25. The memory device of claim 18, wherein:

the memory device comprises a monolithic three dimensional NAND string;

the least one memory film comprises blocking dielectric, a charge trapping layer or floating gate and a tunnel dielectric;

the tunnel dielectric is located between the charge trapping layer or floating gate and the semiconductor channel;

the protrusion comprises a rail or pillar shape select gate channel of a select gate transistor of the NAND string; and

the protrusion contacts a fourth portion of the semiconductor channel that extends generally parallel to the major surface of the substrate and is located over or in the substrate.

26. The memory device of claim 18, wherein the protrusion comprises epitaxially-grown silicon and at least one additional material layer over the epitaxially-grown silicon, wherein the at least one additional material layer comprises at least one of an additional semiconductor material, a metal and a metal nitride.